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參數(shù)資料
| 型號： | SM3-19.44M |
| 廠商： | Connor-Winfield |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MOD TIMING 19.440MHZ STATUM 3 |
| 標準包裝： | 1 |
| 系列： | SM3 |
| 類型： | 定時模塊，系統(tǒng)時鐘 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 19.44MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP 模塊 |
| 包裝： | 管件 |
| 其它名稱： | CW642 SM3 19.44M SM319.44M |
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SM3 Data Sheet #:
TM052
Page 24 of 36 Rev: 06 Date:01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
II. To lock the unit to a reference in autonomous (automatic) mode after power up or reset, the following steps should be taken.
You can also switch from Manual to Autonomous mode directly. When doing so, please ensure that the appropriate references are
available by checking REF_AVAILABLE register (address: 0x0c).
1.
Clear bit1 of CTL_MODE register (address: 0x04). This puts the module in autonomous mode.
2.
Apply signal to the reference inputs
3.
Set the appropriate pull in range by writing to address 0x06
4.
The default bandwidth of 0.098 Hz is appropriate for Stratum 3 operation.
5.
Enable Reference mask for appropriate references by writing a 1 to the reference bit in address 0x0b.
6.
Set priority and revertivity for the input references by writing to the appropriate Ref_Frq_Priority registers (bits 3-0).
7.
Enable all Interrupts by writing 11111111 to address 0x13.
8.
Set the unit to operate in autonomous mode by clearing bit1 of address 0x04
III. Slave Mode Operation:
1.
As a Slave, the module operates in Autonomous mode.
2.
The Bandwidth is set, by default, to 1.6Hz (Bandwidth_PBO register (Address 0x03): 00001011).
3.
Note that bit 4 of the OP_MODE register (Address 0x05) is cleared.
4.
The values in Bits 3-0 of this register have no effect on the operation of the Slave module.
5.
For the Slave module to track the Master accurately, an appropriate Phase Offset value should be written to
PHASE_OFFSET register (Address 0x0e), to compensate for the path delay.
6.
The module will lock to the Cross Reference Input (XREF) from the master.
IV RESET Parameters:
1.
The reset pin should be held low for a minimum of 10 milliseconds to ensure a complete reset occurs.
2.
The SPI interface should not be accessed for a minimum of 1200ms after the reset pin is de-asserted.
Switching Master/Slave designations:
The following steps need to be taken before making Master module a Slave and vice versa.
1.
Copy the value in the PHASE_OFFSET register (Address 0x0e) of the Slave to the Master module’s PHASE_OFFSET
regsiter (Address 0x0e).
2.
Read the contents of Bits 3-0 of the Master’s OP_MODE register (Address 0x05) and copy it into Bits 3-0 of the Slave’s
OP_MODE register (Address 0x05).
3.
It is recommended that the contents of REF(1-4)_FRQ_PRIORITY registers (Address 0x1c-0x1f) and REF_MASK register
(Address 0x0b) from Master be copied to Slave to ensure seamless Master/Slave switches.
Master/Slave switches should be performed with minimal delay between switching the states of each of the two devices.
SM3 Initialization continued
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