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參數(shù)資料
| 型號： | SM3-19.44M |
| 廠商： | Connor-Winfield |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MOD TIMING 19.440MHZ STATUM 3 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SM3 |
| 類型： | 定時模塊，系統(tǒng)時鐘 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 19.44MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP 模塊 |
| 包裝： | 管件 |
| 其它名稱： | CW642 SM3 19.44M SM319.44M |
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SM3 Data Sheet #:
TM052
Page 29 of 36 Rev: 06 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
SM3 Application Note on Interrupts
The SM3/3E module supports eight different interrupts and appears in
INTR_EVENT (0x12) register. Each interrupt can be
individually enabled or disabled via the
INTR_ENABLE (0x13) register. Each bit enables or disables the corresponding interrupt from
asserting the SPI_INT pin. Interrupt events still appear in the
INTR_EVENT (0x12) register independent of their enable state. All
interrupts are cleared once
INTR_EVENT (0x12) register is read. The interrupts are
1. Any reference changing from available to not available
2. Any reference changing from not available to available
3. M/SREF changing from activity to no activity
4. M/SREF changing from no activity to activity
5. DPLL Mode status change
6. Active reference change
7. Loss of Signal
8. Loss of Lock
Interrupts and Reference change in Autonomous mode: Interrupts can be used to determine the cause of a reference change
in autonomous mode. Let us assume that the module is currently locked to REF1. The module switches to REF2 and SPI_INT pin is
asserted. The user reads the
INTR_EVENT (0x12) register.
If the module is operating in autonomous non-revertive mode, the cause can be determined from bits4, 5, 6 and 7. Bit 5 is set to
indicate Active reference change. If Bit 6 is set then the cause of the reference change is Loss of Active Reference. If Bit 7 is set then
the cause of the reference change is a Loss of Lock alarm on the active reference.
If the module is operating in autonomous revertive mode, the cause can be determined from bits 1, 4, 5, 6 and 7. Bit 5 is set to
indicate Active reference change. If Bit6 is set then the cause of the reference change is Loss of Active Reference. If Bit 7 is set then
the cause of the reference change is a Loss of Lock alarm on the active reference. If Bit 1 is set then the cause of the reference
change is the availability of a higher priority reference.
Note: The DPLL Mode Status Change bit (Bit 4) is also set to indicate a change in
DPLL_STATUS (0x11) register, during an interrupt
caused by a reference change. The data in
DPLL_STATUS (0x11) register however is not useful in determining the cause of a
reference change. This is because bits0-2 of this register always reflects the status of the current active reference and hence cannot
be used to determine the status of the last active reference.
Interrupts in Manual Mode: In manual operating mode, when the active reference fails due to a Loss of Signal or Loss of Lock alarm,
an interrupt is generated. For example, in case of a Loss of Signal, bits 4 and 6 of
INTR_EVENT (0x12) register would be set to
indicate Loss of Signal and DPLL Mode Status Change. The user may choose to read the
DPLL_STATUS (0x11) register, though in
manual mode bit6 of
INTR_EVENT (0x12) register is a mirror of bit 0 of DPLL_STATUS (0x11) register. This holds true for a Loss of
Lock alarm, where bit 7 of
INTR_EVENT (0x12) register is a mirror of bit 1 of DPLL_STATUS (0x11) register.
Application Notes continued
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