參數(shù)資料
型號(hào)： SM320C6201BGLPW15
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 33/64頁(yè)
文件大?。?/td> 948K
代理商： SM320C6201BGLPW15
SGUS031B
–
APRIL 2000
–
REVISED AUGUST 2001
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
INPUT AND OUTPUT CLOCKS (CONTINUED)
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 12)
NO.
PARAMETER
C6201B
UNIT
MIN
MAX
1
td(CKO1-SSCLK)
td(CKO1-SSCLK1/2)
td(CKO1-CKO2)
td(CKO1-SDCLK)
P = 1/CPU clock frequency in ns.
*Not production tested.
Delay time, CLKOUT1 edge to SSCLK edge
(P/2) + 0.2
(P/2) + 4.2
ns
2
Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)
(P/2)
–
1
(P/2) + 2.4
ns
3
Delay time, CLKOUT1 edge to CLKOUT2 edge
*(P/2)
–
1
*(P/2) + 2.4
ns
4
Delay time, CLKOUT1 edge to SDCLK edge
(P/2)
–
1
(P/2) + 2.4
ns
4
3
2
1
CLKOUT1
SSCLK
SSCLK (1/2rate)
CLKOUT2
SDCLK
Figure 12. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
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