參數(shù)資料
型號(hào)： SM320C6201BGLPW15
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 47/64頁(yè)
文件大小： 948K
代理商： SM320C6201BGLPW15
SGUS031B
–
APRIL 2000
–
REVISED AUGUST 2001
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles
(see Figure 27)
NO.
C6201B
MIN
UNIT
MAX
2
tw(ILOW)
tw(IHIGH)
Width of the interrupt pulse low
*2P
ns
3
Width of the interrupt pulse high
*2P
ns
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can
be connected to asynchronous inputs.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested.
switching characteristics during interrupt response cycles
§
(see Figure 27)
NO.
PARAMETER
C6201B
MIN
UNIT
MAX
1
tR(EINTH-IACKH)
td(CKO2L-IACKV)
td(CKO2L-INUMV)
td(CKO2L-INUMIV)
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2
×
CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
*Not production tested.
Response time, EXT_INTx high to IACK high
*9P
ns
4
Delay time, CLKOUT2 low to IACK valid
*
–
4
6
ns
5
Delay time, CLKOUT2 low to INUMx valid
6
ns
6
Delay time, CLKOUT2 low to INUMx invalid
*
–
4
ns
Interrupt Number
6
5
4
4
3
2
CLKOUT2
EXT_INTx, NMI
1
Intr Flag
IACK
INUMx
Figure 27. Interrupt Timing
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