參數(shù)資料
型號(hào)： SM89S16R1
廠商： Electronic Theatre Controls, Inc.
英文描述： 8-Bits Micro-controller With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
中文描述： 8位微與64KB的快閃記憶體控制器
文件頁數(shù)： 14/28頁
文件大?。?/td> 416K
代理商： SM89S16R1
SyncMOS Technologies Inc. SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
SM89S16R1 V1.0 JANUARY 2005
14
Figure 12 Sequences and Phases
FIGURE 12 shows the fetch / execute sequences in states and phases for various kinds of instructions. Normally the
program fetches are generated during each machine cycle, even if the instruction being executed doesn’t require it. If
the instruction being executed doesn’t need more code bytes, the CPU simply ignores the extra fetch, and the
PROGRAM COUNTER is incremented accordingly.
Execution of a one-cycle instruction (FIGURE 13A and B) begins during S1 of the machine cycle, when the
OPCODE is latched into INSTRUCTION REGISTER. A second fetch occurs during S4 of the same machine cycle.
Execution is completed at the end of S6 of this machine cycle.
The MOVX instructions take two machine cycles to execute. No program fetch is generated during the second cycle
of a MOVX instruction. This is the only time program fetches are skipped. The fetch/execute sequence for MOVX
instructions is shown in FIGURE13 (D)
The fetch/execute sequences are the same whether the PROGRAM MEMORY is internal or external to the chip.
Execution times do not depend on whether the PROGRAM MEMORY is internal or external.
FIGURE 14 shows the signals and timing involved in program fetches when the program memory is external. If
PROGRAM MEMORY is external, the PROGRAM MEMORY READ STOBE (/PSEN) is normally activated twice
per machine cycle, as shown in FIGURE 14(A).
If an access external DATA MEMORY occurs, as shown in FIGURE 14(B), two (/PSEN) are SKIPPED, because the
address and data bus are being used for DATA MEMORY access.
Note that a DATA MEMORY bus cycle takes twice as much time as PROGRAM MEMORY bus cycle. FIGURE 14
shows the relative time of the address begin emitted at PORT0 and PORT2, and of ALE and /PSEN. ALE is used to
latch the low address byte form PORT0 into the address latch.
When CPU is executing from internal PROGRAM MEMORY, /PSEN is not activated, and program address is not
emitted. However, ALE continues to be activated twice per machine cycle and so is available as clock output signal.
Note, however, that ALE is skipped during the execution of the MOVX instruction.
P1
P2
P1
P2
P1
P2
P1
OSC
(Xtal2)
P2
P1
P2
P1
P2
P1
P2
P1
S1
S2
S3
S4
S5
S6
S1
S2
PHASE
SEQUENCE
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