參數(shù)資料
型號(hào): SM89S16R1
廠商: Electronic Theatre Controls, Inc.
英文描述: 8-Bits Micro-controller With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
中文描述: 8位微與64KB的快閃記憶體控制器
文件頁(yè)數(shù): 20/28頁(yè)
文件大小: 416K
代理商: SM89S16R1
SyncMOS Technologies Inc. SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Internal Data memory
The data memory of SM89S16R1 consists of 1024 bytes internal data memory (256 bytes standard RAM and 768
bytes AUX-RAM). The AUX-RAM is enable by SCONF.1 ($BF.1), and read/write by MOVX
Analog to Digital Converter (ADC)
The ADC block diagram was shown as below:
Those are only 4 pins mirror to Port 2[7:4] at Vin<3:0>. The digital output DATA [11:4] were put into ADCD ($8FH).
And the ADC interrupt vector is 4BH.
The ADC SFR shown as below:
ADSCR ($8EH)
Bit7
Bit6
Bit5
Bit4
Com
Con
ADCSS1
ADCSS0
COM: Read only. When conversion complete, it will be set.
CON: when set, the ADC will conversion continuous, else it will conversion only once.
ADCSS [1:0]: ADC clock select. (ADC_CLK range 500 KHz~2.5 MHz).If over frequency of ADC_CLK, the
conversion data may be unstable.
ADCSS1
ADCSS0
0
0
0
1
1
0
1
1
CH [1:0]: ADC channel select.
CH1
CH0
0
0
0
1
1
0
1
1
ADCD ($8FH)
Bit7
Bit6
Bit5
Bit4
AD.5
AD.4
AD.3
AD.2
*Read Only.
Specifications subject to change without notice contact your sales representatives for the most recent information.
SM89S16R1 V1.0 JANUARY 2005
20
Bit3
CH1
Bit2
CH0
Bit1
Bit0
ADC_CLK
FOSC/8
FOSC/16
FOSC/32
FOSC/64
Input select
CH0
CH1
CH2
CH3
Bit3
AD.1
Bit2
AD.0
Bit1
Bit0
6-bit SA R A D C
V SS
V D D (=V ref)
A D C_CLK
4
V A IN <3:0>{P2.4~P2.7}
CH <2:0>{A D SCR[3:2]}
3
6
D A TA <5:0>
{A D CD [7:2]}
A DCSS1 AD CSS0 A DC_CLK
0 0 Fosc/4
0 1 Fosc/8
1 0 Fosc/16
1 1 Fosc/32
A DCSS[1:0]= {AD SCR[5:4]}
Continuous{A D SCR.6}
Com plete
{A D SCR.7}
Figure 16 ADC Block Diagram
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