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參數(shù)資料
| 型號： | SMFV016 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 16M x 8 Bit SmartMedia Card(16M x 8 位 智能媒體卡) |
| 中文描述： | 16米x 8位SmartMedia卡（1,600 × 8位智能媒體卡） |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | SMFV016 |
SMFV016
SmartMedia
TM
21
Figure 8. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Eras e
Setup command(60H). Only address A
14
to A
23
is valid while A
9
to A
13
is ignored. The Erase Confirm command(D0H) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse
repetition where required. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked.
Figure 8 details the sequence.
60H
Block Add. : A
9
~ A
23
I/O
0
~
7
R/B
Address Input(2Cycle)
I/O
0
Pass
D0H
70H
Fail
t
BERS
READ ID
The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address inpu t of
00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (73H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70H command to the command register, a read cycle output s
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/ B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random r ead
cycle, a read command(00H or 50H) should be given before sequential page read cycle.
SR
Status
Definition
I/O 0
Program / Erase
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O 1
Reserved for Future
Use
"0"
I/O 2
"0"
I/O 3
"0"
I/O 4
"0"
I/O 5
"0"
I/O 6
Device Operation
"0" : Busy "1" : Ready
I/O 7
Write Protect
"0" : Protected "1" : Not Protected
Table2. Status Register Definition
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