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參數(shù)資料
| 型號(hào)： | SN2005118412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 220/271頁(yè) |
| 文件大?。?/td> | 3240K |
| 代理商： | SN2005118412ZHK |
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Introduction
36
September 2005
SCPS110
Table 214. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
DESCRIPTION
I/O
POWER
NAME
NO.
DESCRIPTION
I/O
TYPE
POWER
RAIL
OE
K17
Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data output during host
memory read cycles.
DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports
DMA. The controller asserts OE to indicate TC for a DMA write operation.
O
VCCCB
READY
(IREQ)
E12
Ready. The ready function is provided when the 16-bit PC Card and the host socket are configured for the
memory-only interface. READY is driven low by 16-bit memory PC Cards to indicate that the memory card circuits
are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready
to accept a new data transfer command.
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a controller on the 16-bit
I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested.
I
VCCCB
REG
E13
Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is
limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a
separately accessed section of card memory and is generally used to record card capacity and other
configuration and attribute information.
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card
that supports DMA. The controller asserts REG to indicate a DMA operation. REG is used in conjunction with the
DMA read (IOWR) or DMA write (IORD) strobes to transfer data.
O
VCCCB
RESET
C15
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
O
VCCCB
VS1
VS2
A13
B16
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the
operating voltage of the PC Card.
I/O
VCCCB
WAIT
C12
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle in
progress.
I
VCCCB
WE
G17
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory
PC Cards that employ programmable memory technologies.
DMA terminal count. WE is used as a TC during DMA operations to a 16-bit PC Card that supports DMA. The
controller asserts WE to indicate the TC for a DMA read operation.
O
VCCCB
WP (IOIS16)
A11
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit
memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address
on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is
capable of 16-bit accesses.
DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that
supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA operation.
I
VCCCB
These terminals are reserved for the PCI7402 and PCI8402 controllers.
Table 215. CardBus PC Card Interface System Terminals
A 33-
to 47- series damping resistor (per PC Card specification) is the only external component needed
for terminal C16 (CCLK). If any CardBus PC Card interface system terminal is unused, then the terminal may
be left floating.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
POWER
NAME
NO.
DESCRIPTION
I/O
TYPE
INPUT
OUTPUT
PU/
PD
POWER
RAIL
CCLK
F18
CardBus clock. CCLK provides synchronous timing for all transactions on the
CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG,
CAUDIO, CCD2, CCD1, CVS2, and CVS1 are sampled on the rising edge of
CCLK, and all timing parameters are defined with the rising edge of this signal.
CCLK operates at the PCI bus clock frequency, but it can be stopped in the low
state or slowed down for power savings.
O
PCIO3
VCCCB
CCLKRUN
A11
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an
increase in the CCLK frequency, and by the controller to indicate that the CCLK
frequency is going to be decreased.
I/O
PCII4
PCIO4
PU3
VCCCB
CRST
C15
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers,
and signals to a known state. When CRST is asserted, all CardBus PC Card
signals are placed in a high-impedance state, and the controller drives these
signals to a valid logic level. Assertion can be asynchronous to CCLK, but
deassertion must be synchronous to CCLK.
O
PCII4
PCIO4
PU3
VCCCB
These terminals are reserved for the PCI7402 and PCI8402 controllers.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN200512N | 制造商:Texas Instruments 功能描述: |
| SN200513N | 制造商:Texas Instruments 功能描述: |
| SN200515N | 制造商:Texas Instruments 功能描述: |
| SN200520N | 制造商:Texas Instruments 功能描述: |
| SN200530DR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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