
SN54ABT16265 . . . WD PACKAGE
SN74ABT16265 . . . DL PACKAGE
(TOP VIEW)
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OEA
GND
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
GND
SEL
OE2B
GND
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
GND
OE1B
SN54ABT16265, SN74ABT16265
12-BIT TO 24-BIT MULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS468 – JUNE 1992–REVISED OCTOBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS
77251–1443
Copyright
1992, Texas Instruments Incorporated
1
Members of the Texas Instruments
Widebus
Family
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25
°
C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
Bus-Hold Inputs Eliminate the Need for
External Pullup Resistors
Packaged in Plastic 300-mil Shrink
Small-Outline Packages (DL) and 380-mil
Fine-Pitch Ceramic Flat Packages (WD)
Using 25-mil Center-to-Center Spacings
description
The ’ABT16265 is a 12-bit to 24-bit multiplexed
transceiver used in applications where two
separate data paths must be multiplexed onto, or
demultiplexed from, a single data path. Typical
applications
include
demultiplexing of address and data information in
microprocessor- or bus-interface applications.
This device is also useful in memory-interleaving
applications.
multiplexing
and/or
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The
output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. These control signals also
allow byte-control of the most significant byte and least significant byte for each bus.
Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT16265 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin
count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ABT16265 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74ABT16265 is characterized for operation from –40
°
C to 85
°
C.
Widebus and EPIC-
ΙΙ
B are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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