- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373432 > SN54ABT16843 (Texas Instruments, Inc.) 18-Bit Bus-Interface D-Type Latches With 3-State Outputs(18位總線接口D鎖存器(三態(tài)輸出)) PDF資料下載
參數(shù)資料
| 型號： | SN54ABT16843 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18-Bit Bus-Interface D-Type Latches With 3-State Outputs(18位總線接口D鎖存器(三態(tài)輸出)) |
| 中文描述： | 18位總線接口D類鎖存器與三態(tài)輸出（18位總線接口?鎖存器（三態(tài)輸出）） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 182K |
| 代理商： | SN54ABT16843 |
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MAY 1997
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
, tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
相關PDF資料 |
PDF描述 |
|---|---|
| SN54ABT16853 | Dual 8-Bit to 9-Bit Parity Bus Transceivers(雙8-9奇偶總線收發(fā)器) |
| SN54ABT16863WD | 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN54ABT16952WD | 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN74ABT16952DGG | 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN54ABT16952 | 16-Bit Registered Transceivers With 3-State Outputs(16位記錄收發(fā)器(三態(tài)輸出)) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN54ABT16843_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT16843WD | 制造商:TI 制造商全稱:Texas Instruments 功能描述:18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT16853 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT16853_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT16853_07 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
發(fā)布緊急采購，3分鐘左右您將得到回復。