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參數(shù)資料
| 型號： | SN54ABT854 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit To 9-Bit Parity Bus Transceivers(8-9奇偶總線收發(fā)器) |
| 中文描述： | 8位到第9位奇偶總線收發(fā)器（8-9奇偶總線收發(fā)器） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 142K |
| 代理商： | SN54ABT854 |
SN54ABT854, SN74ABT854
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS170 – FEBRUARY 1991–REVISED OCTOBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
FUNCTION TABLE
INPUTS
OUTPUT AND I/O
FUNCTION
OEB
OEA
CLR
LE
Ai
Bi
A
B
PARITY
ERR
Σ
OF H’s
Odd
Even
Σ
OF L’s
L
H
X
X
NA
NA
A
H
L
NA
A data to B bus and
generate parity
B data to A bus and
check parity
Store error flag
Clear error flag register
H
L
X
L
NA
Odd
Even
X
X
B
NA
NA
H
L
H
X
L
X
H
L
H
L
X
X
H
H
H
H
L
L
NA
X
X
X
L Odd
H Even
Odd
Even
X
X
NA
NA
NA
NA
NC
H
NC
H
L
H
H
H
X
Z
Z
Z
Isolation§
L
L
X
X
NA
NA
A
L
H
NA
A data to B bus and
generate inverted parity
NA = not applicable, NC = no change, X = don’t care
Summation of high-level inputs includes PARITY along with Bi inputs.
Output states shown assume the ERR output was previously high.
§In this mode, the ERR output (when clocked) shows inverted parity of the A bus.
logic symbol
ERR
CLR
OEA
OEB
CLR
11
1
2
A1
3
A2
4
A3
5
A4
10
PARITY
15
PARITY
B5
19
B6
18
B7
17
B8
16
8
OEA
1
OEB
14
6
A5
7
A6
8
A7
8
9
A8
B1
23
1
B2
22
B3
21
B4
20
ERR
Φ
A Bus
B Bus
LE
LE
13
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for DW, JT, and NT packages.
P
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