參數(shù)資料
型號: SN54ABT8996FK
廠商: Texas Instruments, Inc.
英文描述: 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS
中文描述: 10位可尋址掃描港口多點尋址IEEE標(biāo)準(zhǔn)1149.1的JTAG技術(shù)咨詢收發(fā)器
文件頁數(shù): 1/40頁
文件大小: 564K
代理商: SN54ABT8996FK
SN54ABT8996, SN74ABT8996
10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS489C – AUGUST 1994 – REVISED APRIL 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of Texas Instruments Broad
Family of Testability Products Supporting
IEEE Std 1149.1-1990 (JTAG) Test Access
Port (TAP) and Boundary-Scan Architecture
Extend Scan Access From Board Level to
Higher Levels of System Integration
Promote Reuse of Lower-Level
(Chip/Board) Tests in System Environment
Switch-Based Architecture Allows Direct
Connect of Primary TAP to Secondary TAP
Primary TAP Is Multidrop for Minimal Use of
Backplane Wiring Channels
Simple Addressing (Shadow) Protocol Is
Received/Acknowledged on Primary TAP
Shadow Protocols Can Occur in Any of
Test-Logic-Reset, Run-Test/Idle, Pause-DR,
and Pause-IR TAP States to Provide for
Board-to-Board Test and Built-In Self-Test
10-Bit Address Space Provides for Up to
1021 User-Specified Board Addresses
Bypass (BYP) Pin Forces
Primary-to-Secondary Connection Without
Use of Shadow Protocols
Connect (CON) Pin Provides Indication of
Primary-to-Secondary Connection
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
Support Backplane Interface at Primary and
High Fanout at Secondary
Package Options Include Plastic Small-
Outline (DW) and Thin Shrink Small-
Outline (PW) Packages, Ceramic Chip
Carriers (FK), and Ceramic DIPs (JT)
description
The ’ABT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments (TI
) SCOPE
testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan
to facilitate testing of complex circuit assemblies. Unlike most SCOPE
devices, the ASP is not a
boundary-scannable device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Standard
1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.
Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP
signals to a set of secondary TAP signals – for example, to interface backplane TAP signals to a board-level
TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and
secondary TAPs are connected, only a moderate propagation delay is introduced – no storage/retiming
elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE is a trademark of Texas Instruments Incorporated.
17
SN54ABT8996 . . . JT PACKAGE
SN74ABT8996 . . . DW OR PW PACKAGE
(TOP VIEW)
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12 13 14 15 16
A8
A9
V
CC
NC
CON
STDI
STCK
A1
A0
BYP
NC
GND
PTDO
PTCK
SN54ABT8996 . . . FK PACKAGE
(TOP VIEW)
A
A
A
S
S
P
P
N
N
A
A
A
P
S
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27 26
A4
A3
A2
A1
A0
BYP
GND
PTDO
PTCK
PTMS
PTDI
PTRST
A5
A6
A7
A8
A9
V
CC
CON
STDI
STCK
STMS
STDO
STRST
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NC – No internal connection
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