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參數(shù)資料
| 型號： | SN54ABTH16823WD |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 中文描述： | 18位總線接口倒裝3觸發(fā)器態(tài)輸出 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 133K |
| 代理商： | SN54ABTH16823WD |
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
To Eight Other Channels
1D1
1Q1
1CLKEN
1OE
1CLR
2
1
55
54
R
1D
C1
3
CE
56
1CLK
To Eight Other Channels
2D1
2Q1
2CLKEN
2OE
2CLR
27
28
30
42
R
1D
C1
15
CE
29
2CLK
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, V
I
(see Note 1)
Voltage range applied to any output in the high or power-off state, V
O
Current into any output in the low state, I
O
: SN54ABTH16823
–0.5 V to 7 V
–0.5 V to 7 V
–0.5 V to 5.5 V
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96 mA
128 mA
–18 mA
–50 mA
81
°
C/W
74
°
C/W
SN74ABTH16823
Input clamp current, I
IK
(V
I
< 0)
Output clamp current, I
OK
(V
O
< 0)
Package thermal impedance,
θ
JA
(see Note 2): DGG package
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DL package
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Storage temperature range, T
stg
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–65
°
C to 150
°
C
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