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參數(shù)資料
| 型號(hào)： | SN54AC74FK |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| 中文描述： | 雙上升沿觸發(fā)的，有清除和預(yù)設(shè)功能的D型觸發(fā)器 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大小： | 111K |
| 代理商： | SN54AC74FK |
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
μ
m Process
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), Flat
(W), and DIP (J,N) Packages
description
The ’AC74 are dual positive-edge-triggered
D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at D can be changed without affecting the levels
at the outputs.
The SN54AC74 is characterized for operation
over the full military temperature range of –55
°
C
to 125
°
C. The SN74AC74 is characterized for
operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
H
L
L
X
↑
↑
L
X
H
H
H
H
H
L
H
H
L
L
H
H
H
X
Q0
Q0
This configuration is unstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54AC74 . . . FK PACKAGE
(TOP VIEW)
SN54AC74 . . . J OR W PACKAGE
SN74AC74 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1
1
N
2
2
C
2
1
G
N
NC – No internal connection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54AC74J | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| SN54AC74W | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| SN74AC86DB | Low Voltage CMOS Hex Schmitt Inverter With 5 V-Tolerant Inputs; Package: SOIC 14 LEAD; No of Pins: 14; Container: Rail; Qty per Container: 55 |
| SN54AC86J | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| SN54AC86W | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54AC74J | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| SN54AC74W | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| SN54AC86 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| SN54AC86_06 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| SN54AC86FK | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
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