參數資料
型號: SN54LS109J
廠商: Motorola, Inc.
英文描述: LOG CMOS GATE AND QUAD; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
中文描述: 雙JK上升沿觸發(fā)器
文件頁數: 1/4頁
文件大小: 147K
代理商: SN54LS109J
5-181
FAST AND LS TTL DATA
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS109A consists of two high speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise
and fall times of the clock waveform. The JK design allows operation as a D
flip-flop by simply connecting the J and K pins together.
LOGIC DIAGRAM
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
SD
L
H
L
H
H
H
H
CD
H
L
L
H
H
H
H
J
K
Q
Q
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
H
q
q
L
L
H
H
L
q
q
H
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) =
one set-up time prior to the LOW to HIGH clock transition.
SN54/74LS109A
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
相關PDF資料
PDF描述
SN54LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS112D DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS112N DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN54LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
相關代理商/技術參數
參數描述
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SN54LS11J 制造商:Texas Instruments 功能描述:AND Gate 3-Element 3-IN Bipolar 14-Pin CDIP Tube 制造商:Texas Instruments 功能描述:AND GATE 3-ELEM 3-IN BIPOLAR 14CDIP - Rail/Tube
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