參數(shù)資料
型號: SN54LS112A
廠商: Motorola, Inc.
英文描述: DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
中文描述: 雙JK負(fù)邊沿觸發(fā)器
文件頁數(shù): 1/4頁
文件大?。?/td> 147K
代理商: SN54LS112A
5-185
FAST AND LS TTL DATA
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
LOGIC DIAGRAM
(Each Flip-Flop)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
SD
L
H
L
H
H
H
H
CD
H
L
L
H
H
H
H
J
K
Q
Q
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
q
L
H
q
L
H
H
q
H
L
q
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) =
one set-up time prior to the HIGH to LOW clock transition.
SN54/74LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
相關(guān)PDF資料
PDF描述
SN74LS112D DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS112N DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN54LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN54LS113J DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
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