參數(shù)資料
型號(hào): SN54LS165J
廠商: MOTOROLA INC
元件分類(lèi): 通用總線功能
英文描述: BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS
中文描述: LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDIP16
封裝: CERAMIC, DIP-16
文件頁(yè)數(shù): 5/6頁(yè)
文件大?。?/td> 157K
代理商: SN54LS165J
5-282
FAST AND LS TTL DATA
SN54/74LS160A
SN54/74LS161A
SN54/74LS162A
SN54/74LS163A
AC SETUP REQUIREMENTS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tWCP
tW
ts
ts
th
th
trec
*CEP, CET or DATA
Clock Pulse Width Low
25
ns
VCC = 5.0 V
MR or SR Pulse Width
20
ns
Setup Time, other*
20
ns
Setup Time PE or SR
25
ns
Hold Time, data
3
ns
Hold Time, other
0
ns
Recovery Time MR to CP
15
ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time re-
quired between the end of the reset pulse and the clock transi-
tion from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
AC WAVEFORMS
Figure 1. Clock to Output Delays, Count
Frequency, and Clock Pulse Width
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
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