參數(shù)資料
型號(hào)： SN54LS322A
廠商： Motorola, Inc.
英文描述： Octal Buffer/Line Driver with 3-State Outputs; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18
中文描述： 8位移位寄存器帶符號(hào)擴(kuò)展
文件頁數(shù)： 2/4頁
文件大?。?/td> 113K
代理商： SN54LS322A
5-2
FAST AND LS TTL DATA
SN54/74LS322A
BLOCK DIAGRAM
REGISTER
ENABLE
G
S/P
SIGN
EXTEND
SE
D1
DATA
SELECT
DS
D0
CLOCK
CLEAR
OUTPUT
ENABLE
OE
(8)
(9)
(11)
(3)
(19)
(18)
(2)
(1)
(12)
(13)
(7)
(16)
(4)
(17)
CK
D
CLR
Q
Q
CK
D
CLR
Q
Q
CK
D
CLR
Q
Q
CK
D
CLR
Q
Q
A/QA
B/QB
G/QG
H/QH
FOUR
IDENTICAL
CHANNELS
NOT
SHOWN
QH
FUNCTION TABLE
OPERATION
INPUTS
INPUTS/OUTPUTS
QH
′
CLEAR
REGISTER
ENABLE
S/P
SIGN
EXTEND
DATA
SELECT
OUTPUT
ENABLE
CLOCK
A/QA
B/QB
C/QC
H/QH
…
OUTPUT
Clear
L
L
H
X
X
H
X
X
X
X
L
L
X
X
L
L
L
L
L
L
L
L
L
L
Hold
H
H
X
X
X
L
X
QA0
D0
D1
QAn
a
QB0
QAn
QAn
QAn
b
QC0
QBn
QBn
QBn
c
QH0
QGn
QGn
QGn
h
QH0
QGn
QGn
QGn
h
Shift Right
H
H
L
L
H
H
H
H
L
H
L
L
↑
↑
Sign Extend
H
L
H
L
X
L
↑
Load
H
L
L
X
X
X
↑
When the output enable is high, the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or
clearing of the register is not affected. If both the register enable input and the S/P input are low while the clear input is low, the register is
cleared while the eight input/output terminals are disabled to the high-impedance state.
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑
= Transition from LOW to HIGH level
QA0
…
QH0 = the level of QA through QH, respectively, before the indicated steady-state conditions were established
QAn
…
QHn = the level of QA through QH, respectively, before the most recent
↑
transition of the clock
D0, D1 = the level of steady-state inputs at inputs D0 and D1 respectively
a
…
h = the level of steady-state inputs at inputs A through H respectively
相關(guān)PDF資料
PDF描述
SN54LS322J Octal Buffer/Line Driver with 3-State Outputs; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18
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