參數(shù)資料
型號(hào)： SN54LS322A
廠商： Motorola, Inc.
英文描述： Octal Buffer/Line Driver with 3-State Outputs; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18
中文描述： 8位移位寄存器帶符號(hào)擴(kuò)展
文件頁(yè)數(shù)： 4/4頁(yè)
文件大小： 113K
代理商： SN54LS322A
5-4
FAST AND LS TTL DATA
SN54/74LS322A
AC CHARACTERISTICS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
fMAX
tPHL
tPLH
Maximum Clock Frequency
25
35
MHz
CL = 15 pF
Propagation Delay, Clock
to QH
′
26
22
35
33
ns
tPHL
Propagation Delay, Clear
to QH
′
27
35
ns
tPHL
tPLH
Propagation Delay, Clock
to QA–QH
22
16
33
25
ns
RL = 667
tPHL
Propagation Delay, Clear
to QA–QH
22
35
ns
CL = 45 pF,
tPZH
tPZL
Output Enable Time
15
15
35
35
ns
tPHZ
tPLZ
Output Disable Time
15
15
25
25
ns
CL = 5.0 pF
AC SETUP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
tW
tW
ts
ts
Clock Pulse Width HIGH
25
ns
VCC = 5.0 V
Clock Pulse Width LOW
15
ns
Clear Pulse Width LOW
20
ns
Data Setup Time
20
ns
Select Setup Time
15
ns
th
th
trec
Data Hold Time
0
ns
Select Hold Time
10
ns
Recovery Time
20
ns
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
相關(guān)PDF資料
PDF描述
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