參數(shù)資料
型號： SN54LS569J
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS
中文描述： LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDIP20
封裝： CERAMIC, DIP-20
文件頁數(shù)： 3/8頁
文件大小： 260K
代理商： SN54LS569J
5-575
FAST AND LS TTL DATA
SN54/74LS569A
DEFINITION OF FUNCTIONAL TERMS
A, B, C, D
The four programmable data inputs.
CEP
Count Enable Parallel. Can be used to
enable and inhibit counting in high speed
cascaded operation. CEP must be LOW to
count.
CET
Count Enable Trickle. Enables the ripple
carry output for cascaded operation. Must
be LOW to count.
CP
Clock Pulse. All synchronous functions
occur on the LOW-to-HIGH transition of the
clock.
LOAD
Enables parallel load of counter outputs
from data inputs on the next clock edge.
Must be HIGH to count.
U/D
Up/Down Count Control. HIGH counts up
and LOW counts down.
ACLR
Asynchronous Clear. Master reset of
counters to zero when ACLR is LOW,
independent of the clock.
SCLR
Synchronous clear of counters to zero on
the next clock edge when SCLR is LOW.
OE
A HIGH on the output control sets the four
counter outputs in the high impedance, and
a LOW, enables the output.
YA, YB, YC, YD
The four counter outputs.
RCO
Ripple Carry Output. Output will be LOW on
the maximum count on up-count. Upon
down-count, RCO is LOW at 0000.
CCO
Clock Carry Output. While counting and
RCO is LOW, CCO will follow the clock
HIGH-LOW-HIGH transition.
Note: Actual current flow direction shown
LOW-POWER SCHOTTKY INPUT/OUTPUT
CURRENT INTERFACE CONDITIONS
相關(guān)PDF資料
PDF描述
SN74LS623DW OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUT
SN54LS623 Octal Buffer/Line Driver with 3-State Outputs; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500
SN54LS623J Octal Buffer/Line Driver with 3-State Outputs; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500
SN74LS623N OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUT
SN74LS669D SYNCHRONOUS 4-BIT UP/DOWN COUNTER
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