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參數(shù)資料
| 型號(hào)： | SN54LV74W |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-Stage Binary Ripple Counter with Divide-By-2 and Divide-By-5 Sections; Package: SOEIAJ-16; No of Pins: 16; Container: Rail; Qty per Container: 50 |
| 中文描述： | 雙上升沿觸發(fā)的D型觸發(fā)器 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大小： | 137K |
| 代理商： | SN54LV74W |
SN54LV74, SN74LV74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
SN54LV74
VCC = 3.3 V
±
0.3 V
MIN
TYP
PARAMETER
(OUTPUT)
VCC = 5 V
±
0.5 V
MIN
TYP
VCC = 2.7 V
MIN
UNIT
MAX
MAX
MAX
fmax
70
100
11
60
90
18
50
MHz
tpd
PRE or CLR
Q or Q
19
27
34
ns
CLK
10
17
17
26
28
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
SN74LV74
VCC = 3.3 V
±
0.3 V
MIN
TYP
PARAMETER
(OUTPUT)
VCC = 5 V
±
0.5 V
MIN
TYP
VCC = 2.7 V
MIN
UNIT
MAX
MAX
MAX
fmax
70
100
11
60
90
18
50
MHz
tpd
PRE or CLR
Q or Q
19
27
34
ns
CLK
10
17
17
26
28
operating characteristics, T
A
= 25
°
C
PARAMETER
TEST CONDITIONS
VCC
3.3 V
TYP
32
UNIT
Cd
Cpd
Power dissipation capacitance per flip flop
Power dissipation capacitance per flip-flop
CL= 50 pF
CL = 50 pF,
f = 10 MHz
pF
5 V
68
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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