參數資料
型號: SN54LVTZ245
廠商: Texas Instruments, Inc.
英文描述: 3.3V ABT Octal Buffers/Drivers With 3-State Outputs(3.3 ABT 八緩沖器/驅動器(三態(tài)輸出))
中文描述: 3.3生根粉八路緩沖器/驅動器與3態(tài)輸出(3.3 ABT生根粉八緩沖器/驅動器(三態(tài)輸出))
文件頁數: 1/7頁
文件大?。?/td> 149K
代理商: SN54LVTZ245
SN54LVTZ245, SN74LVTZ245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS303C – DECEMBER 1993 – REVISED JANUARY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
High-Impedance State During Power Up
and Power Down
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs
description
These octal bus transceivers are designed
specifically for low-voltage (3.3-V) V
CC
operation,
but with the capability to provide a TTL interface
to a 5-V system environment.
These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the devices so the buses are effectively
isolated.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVTZ245 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVTZ245 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LVTZ245 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
SN54LVTZ245 . . . J PACKAGE
SN74LVTZ245 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
A
A
D
B
B
O
A
G
B
V
C
SN54LVTZ245 . . . FK PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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