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| 型號： | SN74ALVC16843 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18-Bit Bus-Interface D-Type Latches(18位總線接口D鎖存器（三態(tài)輸出）) |
| 中文描述： | 18位總線接口D類鎖存器（18位總線接口?鎖存器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 92K |
| 代理商： | SN74ALVC16843 |
SN74ALVC16843
18-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS275 – JANUARY 1993 – REVISED MARCH 1994
Copyright
1994, Texas Instruments Incorporated
9–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Designed to Facilitate Incident-Wave
Switching for Line Impedances of 50
or Greater
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 18-bit bus-interface D-type latch is designed
for 2.7-V to 3.6-V V
CC
operation.
The SN74ALVC16843 features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The SN74ALVC16843 can be used as two 9-bit
latches or one 18-bit latch. The eighteen latches
are transparent D-type latches. The device has
noninverting data (D) inputs and provides true
data at its outputs.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and
power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In
the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines without need for interface or pullup
components.
The output-enable (OE) input does not affect the internal operations of the latch. Previously stored data can be
retained or new data can be entered while the outputs are in the high-impedance state.
The SN74ALVC16843 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN74ALVC16843 is characterized for operation from –40
°
C to 85
°
C.
DGG OR DL PACKAGE
(TOP VIEW)
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1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1LE
1PRE
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2PRE
2LE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
P
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