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參數(shù)資料
| 型號(hào)： | SN74LS112N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| 中文描述： | LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 147K |
| 代理商： | SN74LS112N |
5-186
FAST AND LS TTL DATA
SN54/74LS112A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°
C
IOH
IOL
Output Current — High
54, 74
–0.4
mA
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
74
0.8
VIK
Input Clamp Diode Voltage
–0.65
–1.5
V
VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
or VIL per Truth Table
VCC = MIN, IOH = MAX, VIN = VIH
74
2.7
3.5
V
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
per Truth Table
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
IIH
Input HIGH Current
J, K
Set, Clear
Clock
20
60
80
μ
A
VCC = MAX, VIN = 2.7 V
J, K
Set, Clear
Clock
0.1
0.3
0.4
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
J, K
Clear, Set, Clk
–0.4
–0.8
mA
VCC = MAX, VIN = 0.4 V
IOS
ICC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Short Circuit Current (Note 1)
–20
–100
mA
VCC = MAX
VCC = MAX
Power Supply Current
6.0
mA
AC CHARACTERISTICS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
fMAX
Maximum Clock Frequency
30
45
MHz
CL = 15 pF
tPHL
Propagation Delay, Clock
Clear, Set to Output
15
20
ns
VCC = 5.0 V
tPLH
15
20
ns
AC SETUP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
tW
ts
th
Clock Pulse Width High
20
ns
VCC = 5.0 V
Clear, Set Pulse Width
25
ns
Setup Time
20
ns
Hold Time
0
ns
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| SN54LS113A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| SN74LS113A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS113ADR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS113AN | 制造商:Motorola Inc 功能描述: |
| SN74LS114ADR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS114AN | 制造商:ONS 功能描述:ON SEMICONDUCTOR NXF7C, NXA5B 制造商:Motorola Inc 功能描述: |
| SN74LS11D | 功能描述:邏輯門 Triple 3-Input Positive-AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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