參數(shù)資料
型號(hào)： SN74LVC1G00YEPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 門電路
英文描述： LVC/LCX/Z SERIES, 2-INPUT NAND GATE, BGA5
封裝： DSBGA-5
文件頁(yè)數(shù)： 15/17頁(yè)
文件大?。?/td> 508K
代理商： SN74LVC1G00YEPR
SN74LVC1G00
SINGLE 2INPUT POSITIVENAND GATE
SCES212T APRIL 1999 REVISED JUNE 2005
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
VLOAD
Open
GND
RL
Data Input
Timing Input
VI
0 V
VI
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPLH
VOH
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V
VOH V
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VM
VI
VM
1.8 V
± 0.15 V
2.5 V
± 0.2 V
3.3 V
± 0.3 V
5 V
± 0.5 V
1 k
500
500
500
VCC
RL
2
× VCC
2
× VCC
6 V
2
× VCC
VLOAD
CL
30 pF
50 pF
0.15 V
0.3 V
V
VCC
3 V
VCC
VI
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2.5 ns
INPUTS
Figure 2. Load Circuit and Voltage Waveforms
相關(guān)PDF資料
PDF描述
SN74LVC1G02DCKTE4 LVC/LCX/Z SERIES, 2-INPUT NOR GATE, PDSO5
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