參數(shù)資料
型號(hào)： SN74LVC1GU04YZTR
廠商： Texas Instruments, Inc.
英文描述： SINGLE INVERTER GATE
中文描述： 單逆變柵極
文件頁(yè)數(shù)： 3/14頁(yè)
文件大?。?/td> 537K
代理商： SN74LVC1GU04YZTR
www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Recommended Operating Conditions
(1)
SN74LVC1GU04
SINGLE INVERTER GATE
SCES215T–APRIL 1999–REVISED JANUARY 2007
RATING
–0.5 to 6.5
0.5 to 6.5
–0.5 to V
CC
+ 0.5
–50
–50
±
50
±
100
206
252
142
132
116
–65 to 150
UNIT
V
V
V
mA
mA
mA
mA
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage range
(2)
Voltage range applied to any output in the high or low state
(2)(3)
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CC
or GND
V
I
< 0
V
O
< 0
DBV package
DCK package
DRL package
YZP package
YZV package
θ
JA
Package thermal impedance
(4)
°
C/W
T
stg
Storage temperature range
°
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of V
is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
(2)
(3)
(4)
MIN
1.65
MAX
5.5
UNIT
V
V
V
V
V
V
CC
V
IH
V
IL
V
I
V
O
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
I
O
= –100
μ
A
I
O
= 100
μ
A
0.75
×
V
CC
0.25
×
V
CC
0
0
5.5
V
CC
–4
–8
–16
–24
–32
V
CC
= 1.65 V
V
CC
= 2.3 V
I
OH
High-level output current
mA
V
CC
= 3 V
V
CC
= 4.5 V
V
CC
= 1.65 V
V
CC
= 2.3 V
4
8
I
OL
Low-level output current
16
24
32
85
mA
V
CC
= 3 V
V
CC
= 4.5 V
T
A
Operating free-air temperature
–40
°
C
(1)
All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number
SCBA004
.
3
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