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參數(shù)資料
| 型號(hào)： | SN74LVCH16374AZRDR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS |
| 中文描述： | 16位邊沿觸發(fā)的D -型觸發(fā)器具有三態(tài)輸出 |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 331K |
| 代理商： | SN74LVCH16374AZRDR |
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
GQL OR ZQL PACKAGE
(TOP VIEW)
J
K
H
G
F
E
D
C
B
A
2
1
3 4
6
5
GRD OR ZRD PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
SN74LVCH16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS757A–DECEMBER 2003–REVISED OCTOBER 2005
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
The SN74LVCH16374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive
transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D)
inputs.
This device is fully specified for partial-power-down applications using I
. The I
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TERMINAL ASSIGNMENTS
(1)
(56-Ball GQL/ZQL Package)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
NC
GND
V
CC
GND
NC
GND
V
CC
GND
NC
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
1CLK
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2CLK
GND
V
CC
GND
NC
GND
V
CC
GND
NC
xxx
(1)
NC – No internal connection
TERMINAL ASSIGNMENTS
(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
1Q1
1Q3
1Q5
1Q7
2Q1
2Q3
2Q5
2Q7
2Q8
NC
1Q2
1Q4
1Q6
1Q8
2Q2
2Q4
2Q6
NC
1OE
NC
V
CC
GND
GND
GND
V
CC
NC
2OE
1CLK
NC
V
CC
GND
GND
GND
V
CC
NC
2CLK
NC
1D2
1D4
1D6
1D8
2D2
2D4
2D6
NC
1D1
1D3
1D5
1D7
2D1
2D3
2D5
2D7
2D8
(1)
NC – No internal connection
2
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