參數(shù)資料
型號: SN74LVCH16374AZRDR
廠商: Texas Instruments, Inc.
英文描述: 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
中文描述: 16位邊沿觸發(fā)的D -型觸發(fā)器具有三態(tài)輸出
文件頁數(shù): 5/15頁
文件大?。?/td> 331K
代理商: SN74LVCH16374AZRDR
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see
Figure 1
)
SN74LVCH16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS757A–DECEMBER 2003–REVISED OCTOBER 2005
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
(1)
MAX
UNIT
I
OH
= –100
μ
A
I
OH
= –4 mA
I
OH
= –8 mA
1.65 V to 3.6 V
1.65 V
2.3 V
2.7 V
3 V
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
2.7 V
3 V
3.6 V
V
CC
– 0.2
1.2
1.7
2.2
2.4
2.2
V
OH
V
I
OH
= –12 mA
I
OH
= –24 mA
I
OL
= 100
μ
A
I
OL
= 4 mA
I
OL
= 8 mA
I
OL
= 12 mA
I
OL
= 24 mA
V
I
= 0 to 5.5 V
V
I
= 0.58 V
V
I
= 1.07 V
V
I
= 0.7 V
V
I
= 1.7 V
V
I
= 0.8 V
V
I
= 2 V
V
I
= 0 to 3.6 V
(3)
V
I
or V
O
= 5.5 V
V
O
= 0 to 5.5 V
V
I
= V
CC
or GND
3.6 V
V
I
5.5 V
(4)
One input at V
CC
– 0.6 V,
V
I
= V
CC
or GND
V
O
= V
CC
or GND
0.2
0.45
0.7
0.4
0.55
±
5
V
OL
V
I
I
μ
A
(2)
1.65 V
(2)
45
2.3 V
I
I(hold)
–45
75
–75
μ
A
3 V
3.6 V
0
3.6 V
±
500
±
10
±
10
20
20
500
I
off
I
OZ
μ
A
μ
A
I
CC
I
O
= 0
3.6 V
μ
A
I
CC
C
i
C
o
Other inputs at V
CC
or GND
2.7 V to 3.6 V
3.3 V
3.3 V
μ
A
pF
pF
5
6.5
(1)
(2)
(3)
(4)
All typical values are at V
= 3.3 V, T
= 25
°
C.
This information was not available at the time of publication.
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
This applies in the disabled state only.
V
CC
= 1.8 V
0.15 V
MIN
V
CC
= 2.5 V
±
0.2 V
MIN
V
CC
= 3.3 V
±
0.3 V
MIN
V
CC
= 2.7 V
UNIT
MAX
MAX
MIN
MAX
150
MAX
150
f
clock
t
w
t
su
t
h
Clock frequency
Pulse duration, CLK high or low
Setup time, data before CLK
Hold time, data after CLK
(1)
(1)
MHz
ns
ns
ns
(1)
(1)
3.3
1.9
1.1
3.3
1.9
1.1
(1)
(1)
(1)
(1)
(1)
This information was not available at the time of publication.
5
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