R0(LSB) R1 R2 R3 R4 R5 R6 R7(MSB)" />
參數(shù)資料
型號(hào)： SN75LVDS83CZQLR
廠(chǎng)商： Texas Instruments
文件頁(yè)數(shù)： 6/27頁(yè)
文件大小： 0K
描述： IC FLATLINK TX 10-85MHZ 56BGA
標(biāo)準(zhǔn)包裝： 1,000
系列： *
SN75LVDS83C
24-bpc GPU
R0(LSB)
R1
R2
R3
R4
R5
R6
R7(MSB)
G0(LSB)
G1
G2
G3
G4
G5
G6
G7(LSB)
B0(LSB)
B1
B2
B3
B4
B5
B6
B7(MSB)
HSYNC
VSYNC
ENABLE
RSVD (Note C)
CLK
FORMAT1
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
Y3M
Y3P
CLKOUTM
CLKOUTP
FPC
Cable
V
D
G
P
U
IO
1.8V or 2.5V
or 3.3V
G
N
D
C1
100
LVDS
timing
Controller
(8bpc, 24bpp)
100
to column
driver
to row driver
Main Board
IO
V
C
L
K
S
E
L
Rpullup
Rpulldown
(See Note B)
V
C
L
V
D
S
V
C
P
L
V
C
G
N
D
3.3V
C2
C3
3.3V
SHTDN
4.8k
24-bpp LCD Display
FORMAT2 (See Note A)
D27
D5
D0
D1
D2
D3
D4
D6
D10
D11
D7
D8
D9
D12
D13
D14
D16
D17
D15
D18
D19
D20
D21
D22
D24
D25
D26
D23
CLKIN
Panel
connector
Main
board
connector
SLLSE66A
– OCTOBER 2010 – REVISED SEPTEMBER 2011
Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each
color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of
each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by
checking the LCD display data sheet.
Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the
dominate data format for LCD panels.
Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
C1: decoupling cap for the VDDIO supply; install at least 1x0.01
F.
C2: decoupling cap for the VDD supply; install at least 1x0.1
F and 1x0.01F.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1
F and 1x0.01F.
Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.
Note D. RSVD must be driven to a valid logic level. All unused SN75LVDS83C inputs must be tied to a valid logic
level.
Figure 11. 24-Bit Color Host to 24-bit LCD Panel Application
14
Copyright
2010–2011, Texas Instruments Incorporated
Product Folder Link(s): SN75LVDS83C
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