R7(MSB) G2 G3 G4 G5 G6 G7" />
參數(shù)資料
型號: SN75LVDS83CZQLR
廠商: Texas Instruments
文件頁數(shù): 9/27頁
文件大小: 0K
描述: IC FLATLINK TX 10-85MHZ 56BGA
標準包裝: 1,000
系列: *
SN75LVDS83C
24-bpp GPU
R2
R3
R4
R5
R6
R7(MSB)
G2
G3
G4
G5
G6
G7(MSB)
B2
B3
B4
B5
B6
B7(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
Y3M
Y3P
FPC
Cable
V
D
G
P
U
IO
1.8V or 2.5V
or 3.3V
G
N
D
IO
V
C
L
K
S
E
L
Rpullup
Rpulldown
(See Note C)
(See Note A)
V
C
LV
D
S
V
C
P
L
V
C
G
N
D
3.3V
C2
C1
C3
3.3V
100
LVDS
timing
Controller
(6-bpc, 18-bpp)
l
t
100
to column
driver
to row driver
Main Board
18-bpp LCD Display
SH
TDN
4.8k
Panel
connector
Main
board
connector
R0 and R1: NC
(See Note B)
B0 and B1: NC
(See Note B)
G0 and G1: NC
(See Note B)
B0 and B1: NC
(See Note B)
SLLSE66A
– OCTOBER 2010 – REVISED SEPTEMBER 2011
Note A. Leave output Y3 NC.
Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down
to18-bit per pixel.
NoteC.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
C1: decoupling cap for the VDDIO supply; install at least 1x0.01
F.
C2: decoupling cap for the VDD supply; install at least 1x0.1
F and 1x0.01F.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1
F and 1x0.01F.
Figure 14. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application
Copyright
2010–2011, Texas Instruments Incorporated
17
Product Folder Link(s): SN75LVDS83C
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