參數(shù)資料
型號(hào): SP3243UCT
元件分類: RS-232
英文描述: 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
中文描述: 5V的高速RS - 232收發(fā)器與0.1uF電容
文件頁數(shù): 10/24頁
文件大?。?/td> 288K
代理商: SP3243UCT
Date: 5/25/04
SP3223U/3243U +3.0V to +5.5V RS-232 Transceivers
10
Copyright 2004 Sipex Corporation
DESCRIPTION
The SP3223U and SP3243U transceivers
meet the EIA/TIA-232 and ITU-T V.28/V.24
communication protocols and can be
implemented in battery-powered, portable, or
hand-held applications such as notebook or
palmtop computers. The SP3223U and SP3243U
devices feature Sipex's proprietary and patented
(U.S.-- 5,306,954) on-board charge pump cir-
cuitry that generates
±
5.5V RS-232 voltage lev-
els from a single +3.0V to +5.5V power supply.
The SP3223U and SP3243U devices can operate
at a data rate of 1000kbps fully loaded.
The SP3223U is a 2-driver/2-receiver device,
and the SP3243U is a 3-driver/5-receiver device,
ideal for portable or hand-held applications. The
SP3243U includes one complementary
always-active receiver that can monitor an
external device (such as a modem) in shutdown.
This aids in protecting the UART or serial
controller IC by preventing forward biasing
of the protection diodes where V
CC
may be
disconnected.
The SP3223U and SP3243U series is an ideal
choice for power sensitive designs. The SP3223U
and SP3243U devices feature AUTO ON-LINE
circuitry which reduces the power supply drain
to a 1
μ
A supply current. In many portable or
hand-held applications, an RS-232 cable can be
disconnected or a connected peripheral can be
turned off. Under these conditions, the internal
charge pump and the drivers will be shut down.
Otherwise, the system automatically comes
online. This feature allows design engineers to
address
power
without major design changes.
saving
concerns
THEORY OF OPERATION
The SP3223U and SP3243U series is made up of
four basic circuit blocks:
1. Drivers
2. Receivers
3. the Sipex proprietary charge pump, and
4. AUTO ON-LINE
circuitry.
Drivers
The drivers are inverting level transmitters that
convert TTL or CMOS logic levels to 5.0V EIA/
TIA-232 levels with an inverted sense relative to
the input logic levels. Typically, the RS-232
output voltage swing is +5.4V with no load and
+5V minimum fully loaded. The driver outputs
are protected against infinite short-circuits to
ground without degradation in reliability. These
drivers comply with the EIA-TIA-232-F and all
previous RS-232 versions. Unused drivers in-
puts should be connected to GND or V
CC
.
The drivers have a minimum data rate of
1000kbps fully loaded with 3k
in parallel with
250pF, ensuring compatibility with PC-to-PC
communication software.
Figure 16. Interface Circuitry Controlled by Micropro-
cessor Supervisory Circuit
SP3243U
28
24
2
1
27
3
26
5K
5K
5K
5K
5K
GND
C1+
C1-
C2+
C2-
T
1
IN
V+
V-
V
CC
14
13
12
20
19
18
17
16
15
0.1
μ
F
0.1
μ
F
0.1
μ
F
+
C2
C5
C1
+
+
C3
C4
+
+
0.1
μ
F
0.1
μ
F
9
10
11
4
5
6
7
8
RS-232
RS-232
23
22
21
V
CC
25
R
1
OUT
R
1
IN
T
2
OUT
R
2
OUT
T
2
IN
T
3
IN
T
3
OUT
T
1
OUT
R
2
IN
R
3
IN
R
4
IN
R
5
IN
R
2
OUT
R
3
OUT
R
4
OUT
R
5
OUT
ONLINE
SHUTDOWN
STATUS
UART
or
Serial
μ
C
SupeP
IC
TxD
RTS
DTR
RxD
CTS
DSR
DCD
RI
V
CC
VIN
RESET
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