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參數(shù)資料
| 型號： | SP3243UCT |
| 元件分類： | RS-232 |
| 英文描述： | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| 中文描述： | 5V的高速RS - 232收發(fā)器與0.1uF電容 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 288K |
| 代理商： | SP3243UCT |
Date: 5/25/04
SP3223U/3243U +3.0V to +5.5V RS-232 Transceivers
12
Copyright 2004 Sipex Corporation
Receivers are active when the AUTO ON-LINE
circuitry is enabled or when in shutdown.
During the shutdown, the receivers will continue
to be active. If there is no activity present at the
receivers for a period longer than 100
μ
s or when
SHUTDOWN is enabled, the device goes into a
standby mode where the circuit draws 1
μ
A.
Driving EN to a logic HIGH forces the outputs of
the receivers into high-impedance. The truth
table logic of the SP3223U and SP3243U driver
and receiver outputs can be found in Table 2.
The SP3243U includes an additional non-in-
verting receiver with an output R
OUT. R
OUT
is an extra output that remains active and
monitors activity while the other receiver
outputs are forced into high impedance.
This allows Ring Indicator (RI) from a
peripheral to be monitored without forward
biasing the TTL/CMOS inputs of the other
devices connected to the receiver outputs.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, an internal 5K
pulldown resistor
to ground will commit the output of the receiver
to a HIGH state.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply
consists of a regulated dual charge pump that
provides output voltages 5.5V regardless of the
input voltage (V
) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. This oscillator controls the four phases
of the voltage shifting. A description of each
phase follows.
Phase 1
— V
charge storage — During this phase of
the clock cycle, the positive side of capacitors
C
and C
are initially charged to V
. C
l
then switched to GND and the charge in C
transferred to C
V
, the voltage potential across capacitor C
2
is
now 2 times V
CC
.
+
is
–
is
–
. Since C
+
is connected to
Phase 2
— V
transfer — Phase two of the clock
connects the negative terminal of C
to the V
SS
storage capacitor and the positive terminal of C
2
to GND. This transfers a negative generated
voltage to C
. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C
, the positive side of capacitor C
is switched
to V
CC
and the negative side is connected to
GND.
Phase 3
— V
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
produces –V
in the negative
terminal of C
, which is applied to the negative
side of capacitor C
. Since C
voltage potential across C
2
is 2 times V
CC
.
+
is at V
CC
, the
Phase 4
— V
transfer — The fourth phase of the clock
connects the negative terminal of C
to GND,
and transfers this positive generated voltage
across C
to C
, the V
storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C
, the
positive side of capacitor C
is switched to V
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
Since both V
+
and V
–
are separately generated
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP3243UCY | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| SP3243UEA | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| SP3243U | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| SP3223U | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| SP3223UCA | Surround-Sound CODEC IC; IC Function:Surround-Sound CODEC IC; Package/Case:28-SSOP; Leaded Process Compatible:No; No. of Bits:24; No. of Channels:3; Operating Temp. Min:-10 C; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP3243UCT/TR | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:High Speed Intelligent +3.0V to +5.5V RS-232 Transceivers |
| SP3243UCY | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:High Speed Intelligent +3.0V to +5.5V RS-232 Transceivers |
| SP3243UCY/TR | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:High Speed Intelligent +3.0V to +5.5V RS-232 Transceivers |
| SP3243UEA | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:High Speed Intelligent +3.0V to +5.5V RS-232 Transceivers |
| SP3243UEA/TR | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:High Speed Intelligent +3.0V to +5.5V RS-232 Transceivers |
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