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參數(shù)資料
| 型號： | SP334ET |
| 元件分類： | RS-232 |
| 英文描述： | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| 中文描述： | 5V的高速RS - 232收發(fā)器與0.1uF電容 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 155K |
| 代理商： | SP334ET |
SP334DS/10
Programmable RS-232/RS-485 Transceiver
8
Copyright 2000 Sipex Corporation
THEORY OF OPERATION
The
SP334
is made up of four separate circuit
blocks — the charge pump, drivers, receivers,
and decoder. Each of these circuit blocks is
described in more detail below.
Charge–Pump
The charge pump is a
Sipex
–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 10V
power supplies. Figure 17(a) shows the
waveform found on the positive side of capcitor
C2, and figure 17(b) shows the negative side of
capcitor C2. There is a free–running oscillator
that controls the four phases of the voltage
shifting. A description of each phase follows.
Phase 1
— V
charge storage —During this phase of
the clock cycle, the positive side of capacitors
C
and C
are initially charged to +5V. C
l
then switched to ground and charge on C
transferred to C
+5V, the voltage potential across capacitor C
2
is now 10V.
+
is
–
is
–
. Since C
+
is connected to
Phase 2
— V
transfer — Phase two of the clock
connects the negative terminal of C
to the V
SS
storage capacitor and the positive terminal of C
2
to ground, and transfers the generated –l0V to
C
. Simultaneously, the positive side of capaci-
tor C
is switched to +5V and the negative side
is connected to ground.
Phase 3
— V
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
produces –5V in the negative
terminal of C
, which is applied to the negative
side of capacitor C
. Since C
voltage potential across C
2
is l0V.
+
is at +5V, the
Phase 4
— V
transfer — The fourth phase of the
clock connects the negative terminal of C
to
ground and transfers the generated l0V across
C
to C
, the V
storage capacitor. Again,
simultaneously with this, the positive side of
Figure 13. Charge Pump Phase 1.
Figure 14a. Charge Pump Phase 2.
capacitor C
is switched to +5V and the negative
side is connected to ground, and the cycle begins
again.
Since both V+ and V
–
are separately generated
from V
in a no–load condition, V+ and V
–
will
be symmetrical. Older charge pump approaches
that generate V
–
from V+ will show a decrease
in the magnitude of V
–
compared to V+ due to
the inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors
must be a minimum of 0.1
μ
F with a 16V
breakdown rating.
External Power Supplies
For applications that do not require +5V only,
external supplies can be applied at the V+ and
V
–
pins. The value of the external supply volt-
ages must be no greater than
±
l0V. The current
drain for the
±
10V supplies is used for RS232.
For the RS-232 driver the current requirement
will be 3.5mA per driver. The external power
supplies should provide a power supply se-
quence of :+l0V, then +5V, followed by –l0V.
Drivers
The
SP334
has three independent RS-232 single-
ended drivers and two differential RS-485
drivers. Control for the mode selection is done
by the RS-232/RS-485 select pin. The drivers
are pre-arranged such that for each mode of
V
CC
= +5V
–5V
–5V
+5V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
+
+
–
–
–
–
V
CC
= +5V
–10V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
+
+
–
–
–
–
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