7
P
Rev. 2/15/01
SP6120 Low Voltage, AnyFET
TM
, Synchronous, Buck Controller Copyright 2001 Sipex Corporation
FEATURES
General Overview
The SP6120 is a constant frequency, voltage
mode PWM controller for low voltage, DC/DC
step down converters. It has a main loop where
an external resistor (R
OSC
) sets the frequency and
the driver is controlled by the comparison of an
error amp output (COMP) and a 1V ramp signal.
The error amp has a transconductance of 600
μ
S,
an output impedance of 3 M
, an internal pole at
2 MHz and a 1.25V reference input. Although
the main control loop is capable of 0% and 100%
duty cycle, its response time is limited by the
external component selection. Therefore, a sec-
ondary loop, including a window comparator
positioned 3% above and below the reference,
has been added to insure fast response to line and
load transients. A unique “Ripple & Frequency
Independent” algorithm, added to the secondary
loop, insures that the window comparator does
not interfere with the main loop during normal
operation. In addition to receiving driver com-
mands from the main and secondary loops, the
Driver Logic is also controlled by the Program-
ming Logic, Fault Logic and Zero Crossing
Comparator. The Programming Logic tells the
Driver Logic whether the controller is using a
PFET or NFET high side driver as well as whether
the controller is operating in continuous or dis-
continuous mode. The Fault Logic holds the
high and low side drivers off if V
CC
dips below
2.7V, if an over current condition exists, or if the
part is disabled through the ENABLE pin. The
Zero Crossing Comparator turns the lower driver
off if the conduction current reaches zero and the
Driver Logic has made an attempt to turn the
lower driver on and the Programming Logic is
set for discontinuous mode. Lastly, the 4
driv-
ers have internal gate non-overlap circuitry and
are designed to drive MOSFETs associated
with converter designs in the 5A to 10A range.
Typically the high side driver is referenced to the
SWN pin; further improving the efficiency and
performance of the converter.
ENABLE
Low quiescent mode or “Sleep Mode” is initi-
ated by pulling the ENABLE pin below 600mV.
The ENABLE pin has an internal 4
μ
A pull-up
current and does not require any external inter-
face for normal operation. If the ENABLE pin is
driven from a voltage source, the voltage must
be above 1.3V in order to guarantee proper
“awake” operation. Assuming that V
CC
is above
2.85V, the SP6120 transitions from “Sleep
Mode” to “Awake Mode” in about 20
μ
s to 30
μ
s
and from “Awake Mode” to “Sleep Mode” in a
few microseconds. SP6120 quiescent current in
sleep mode is 20
μ
A maximum. During Sleep
Mode, the high side and low side MOSFETs are
turned off and the COMP and SS pins are held
low.
UVLO
Assuming that the ENABLE pin is either pulled
high or floating, the voltage on the V
CC
pin then
determines operation of the SP6120. As V
CC
rises, the UVLO block monitors V
CC
and keeps
the high side and low side MOSFETs off and the
COMP and SS pins low until V
CC
reaches 2.85V.
If no faults are present, the SP6120 will initiate
a soft start when V
CC
exceeds 2.85V. Hysteresis
(about 100mV) in the UVLO comparator pro-
vides noise immunity at start-up.
Soft Start
(see figures on next page)
Soft start is required on step-down controllers to
prevent excess inrush current through the power
train during start-up. Typically this is managed
by sourcing a controlled current into a program-
ming capacitor (on the SS pin) and then using the
voltage across this capacitor to slowly ramp up
either the error amp reference or the error amp
output (COMP). The control loop creates nar-
row width driver pulses while the output voltage
is low and allows these pulses to increase to their
steady-state duty cycle as the output voltage
increases to its regulated value. As a result of
controlling the inductor volt*second product
during startup, inrush current is also controlled.