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參數(shù)資料
| 型號(hào)： | SP708 |
| 英文描述： | Low Power Microprocessor Supervisory Circuits |
| 中文描述： | 低功耗微處理器監(jiān)控電路 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 197K |
| 代理商： | SP708 |
11
SP705DS/09
SP705 Low Power Microprocessor Supervisory Circuits
Copyright 2000 Sipex Corporation
Power-Fail Comparator
The power-fail comparator can be used for
various purposes because its output and
noninverting input are not internally connected.
The inverting input is internally connected to a
1.25V reference.
To build an early-warning circuit for power
failure, connect the PFI pin to a voltage divider
as shown in
Figure 16
. Choose the voltage
divider ratio so that the voltage at PFI falls
below 1.25V just before the +5V regulator drops
out. Use PFO to interrupt the
μ
P so it can
prepare for an orderly power-down.
Manual Reset
The manual-reset input (MR) allows RESET to
be triggered by a pushbutton switch. The switch
is effectively debounced by the 140ms mini-
mum RESET pulse width. MR is TTL/CMOS
logic compatible, so it can be driven by an
external logic line. MR can be used to force a
watchdog timeout to generate a RESET pulse
in the
SP705/706/813L/813M
. Simply connect
WDO to MR.
Ensuring a Valid RESET Output Down to
V
CC
= 0V
When V
CC
falls below 1V, the
SP705/706/707/
708
RESET output no longer sinks current, it
becomes an open circuit. High-impedance
CMOS logic inputs can drift to undetermined
voltages if left undriven. If a pull-down resistor
is added to the RESET pin, any stray charge or
leakage currents will be shunted to ground,
holding RESET LOW. The resistor value is not
critical. It should be about 100K
, large enough
not to load RESET and small enough to pull
RESET to ground.
Monitoring Voltages Other Than the
Unregulated DC Input
Monitor voltages other than the unregulated DC
by connecting a voltage divider to PFI and
adjusting the ratio appropriately. If required,
add hysteresis by connecting a resistor (with a
value approximately 10 times the sum of the
two resistors in the potential divider network)
between PFI and PFO. A capacitor between PFI
and GND will reduce the power-fail circuit's
PFI
PFO
V
CC
+5V
GND
RESET
to
μ
P
MR
+12V
1M
1%
130K
1%
Figure 17. Monitoring Both +5V and +12V Power
Supplies
GND
GND
RESET
INTERRUPT
I/O LINE
NMI
V
CC
RESET
PFO
PFI
R
2
R
1
Unregulated DC
Power Supply
Regulated +5V
Power Supply
V
CC
0.1
μ
F
PFI
μ
P
WDO
PUSHBUTTON
SWITCH
MR
SP705
SP813L
Figure 16. Typical Operating Circuit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP708CN | Low Power Microprocessor Supervisory Circuits |
| SP708CP | Low Power Microprocessor Supervisory Circuits |
| SP708CU | Low Power Microprocessor Supervisory Circuits |
| SP708EN | Low Power Microprocessor Supervisory Circuits |
| SP706 | Low Power Microprocessor Supervisory Circuits(低功耗，微處理器監(jiān)控電路) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP708CN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Low Power Microprocessor Supervisory Circuits |
| SP708CN-L | 功能描述:監(jiān)控電路 LOW PWR MICROPROCESSOR RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP708CN-L/TR | 功能描述:監(jiān)控電路 LOW PWR MICROPROCESSOR RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP708CP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Low Power Microprocessor Supervisory Circuits |
| SP708CP-L/TR | 制造商:EXAR 制造商全稱:EXAR 功能描述:Low Power Microprocessor Supervisory Circuits |
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