參數(shù)資料
型號(hào): SP7800AJN
英文描述: 12-Bit 3ms Sampling A/D Converter
中文描述: 12位為3ms采樣A / D轉(zhuǎn)換器
文件頁(yè)數(shù): 3/13頁(yè)
文件大?。?/td> 171K
代理商: SP7800AJN
SP7800ADS/02
SP7800A 12-Bit 3
μ
s Sampling A/D Converter
3
Copyright 2000 Sipex Corporation
SPECIFICATIONS (continued)
T
A
= 25
°
C, Sampling Frequency, f
8
, = 333kHz, V
S
= +5V, unless otherwise specified.
PARAMETER
AC ACCURACY
Signal to (Noise + Distortion) Ratio
–J
–K
Signal to Noise Ratio (SNR)
–J
–K
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
–J
–K
Overvoltage Recovery
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
Data Coding
V
OL
V
OH
I
LEAKAGE
(High-Z State)
POWER SUPPLY REQUIREMENTS
Rated Voltage
Current
Power Consumption
ENVIRONMENTAL AND MECHANICAL
Specification
–J, –K
MIN .
TYP.
MAX .
UNITS
CONDITIONS
T
MIN
T
A
T
MAX
f
IN
= 47kHz
67
69
70
71.0
dB
dB
f
IN
= 47kHz
68
70
71
71.5
dB
dB
13
150
ns
ps, rms
Note 5
130
150
150
ns
ns
ns
Note 6
T
MIN
T
A
T
MAX
–0.3
+2.4
–5
+5
+0.8
+5.3
V
V
μ
A
μ
A
Parallel; 12-bit or 8-bit/4-bit
Binary; Offset Binary
DGND
+2.4
±
0.1
+0.4
V
DD
±
V
V
I
SINK
= 1.6mA
I
SOURCE
= 1.6mA
μ
A
+4.75
+5.0
18
90
+5.25
21
V
V
S
(V
SA
and V
SD
)
I
S
mA
mW
0
+70
°
C
Storage
Package
–_N
–_S
–65
+150
°
C
24–pin Narrow DIP
24–pin SOIC
NOTES
1.
2.
Adjustable to zero with external potentiometer.
LSB means Least Significant Bit. For SP7800A, 1LSB = 2.44mV for
±
5V range, 1 LSB = 4.88mV for
±
10V range.
Measured at mid-range, between 4.75 < V
< 5.25 volts.
All specifications in dB are referred to a full-scale input, either
±
10V or
±
5V.
For full-scale step input, 12-bit accuracy attained in specified time.
Recovers to specified performance in specified time after 2 x F
S
input overvoltage.
3.
4.
5.
6.
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