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參數資料
| 型號： | SP7800AJN |
| 英文描述： | 12-Bit 3ms Sampling A/D Converter |
| 中文描述： | 12位為3ms采樣A / D轉換器 |
| 文件頁數： | 9/13頁 |
| 文件大?。?/td> | 171K |
| 代理商： | SP7800AJN |
SP7800ADS/02
SP7800A 12-Bit 3
μ
s Sampling A/D Converter
9
Copyright 2000 Sipex Corporation
R/C
BUSY
Converter
Mode
Data
BUS
Acquire
Convert
Acquire
Convert
Data Valid
Hi-Z State
Hi-Z State
Data Valid
t
W
t
DBC
t
B
t
DBE
t
A
t
C
t
AP
t
HDR
and t
HL
t
DB
Figure 5. Convert Mode Timing — R/C Pulse LOW, Outputs Enabled After Conversion
the
SP7800A.
These potential system problem sources
are particularly important to consider when develop-
ing a new system, and looking for the causes of errors
in breadboards.
First, care should be taken to avoid glitches during
critical times in the sampling and conversion process.
Since the
SP7800A
has an internal sample/hold func-
tion, the signal that puts it into the hold state (R/C going
LOW) is critical, as it would be on any sample/hold
amplifier. The R/C falling edge should be sharp (5 to
10ns), have low jitter and minimal ringing, especially
during the 20ns after it falls.
Although not normally required, it is also good prac-
tice to avoid glitches from coupling to the
SP7800A
while bit decisions are being made. Since the above
discussion calls for a fast, clean rise and fall on R/C, it
makes sense to keep the rising edge of the convert
pulse outside the time when bit decisions are being
made. In other words, the convert pulse should either
be short (under 100ns so that it transitions before the
MSB decision), or relatively long (over 2.75
μ
s to
transition after the LSB decision).
Next, although the data outputs are forced into a Hi-Z
state during conversion, fast bus transients can still be
capacitively coupled into the
SP7800A.
If the data bus
experiences fast transients during conversion, these
transients can be attenuated by adding a logic buffer to
the data outputs. The BUSY output can be used to
enable the buffer.
Figure 6. Read Mode Timing — R/C Pulse HIGH, Outputs Enabled Only When R/C is High
R/C
BUSY
Converter
Mode
Data
BUS
Acquire
Convert
Acquire
Convert
Data
Valid
Hi-Z State
Hi-Z State
t
W
t
DBC
t
B
t
DBE
t
A
t
C
t
AP
t
HDR
and t
HL
t
AP
Data
Valid
Hi-Z State
t
DD
相關PDF資料 |
PDF描述 |
|---|---|
| SP7800AJS | 12-Bit 3ms Sampling A/D Converter |
| SP7800AKN | 12-Bit 3ms Sampling A/D Converter |
| SP7800AKS | 12-Bit 3ms Sampling A/D Converter |
| SP782 | Programmable Charge Pump |
| SP782CP | Programmable Charge Pump |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SP7800AJS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit 3ms Sampling A/D Converter |
| SP7800AKN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit 3ms Sampling A/D Converter |
| SP7800AKS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit 3ms Sampling A/D Converter |
| SP7805AIS WAF | 制造商:Texas Instruments 功能描述: |
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