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| 型號(hào)： | SP791EK |
| 英文描述： | Evaluation Board Manual |
| 中文描述： | 評(píng)估板手冊(cè) |
| 文件頁(yè)數(shù)： | 10/19頁(yè) |
| 文件大?。?/td> | 202K |
| 代理商： | SP791EK |
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SP791DS/08 SP791 Low Power Microprocessor Supervisory with Battery Switch-Over
Copyright 2000 Sipex Corporation
10
WATCHDOG FUNCTION
The watchdog monitors
μ
P activity via the
Watchdog Input (WDI). If the
μ
P becomes in-
active over a period of time, WDO and WDPO
are asserted
.
To use the watchdog functon, connect WDI to a
bus line or
μ
P I/O line. If WDI remains high or
low for longer than the watchdog timeout
period (1.6sec nominal), WDPO and WDO are
asserted, indicating a software fault or idle
condition.
WATCHDOG INPUT
A change of logic state (minimum 100ns dura-
tion) at WDI during the watchdog period will
reset the watchdog timer. The watchdog default
timeout is 1.6sec. To select an alternative
timeout period, connect an external capacitor
from SWT to GND.
To disable the watchdog function, leave WDI
floating. An internal impedance network (100k
equivalent at WDI) biases WDI to approximately
1.6V. Internal comparators detect this level and
disable the watchdog timer. When Vcc is below
the reset threshold, the watchdog function is dis-
abled and WDI is disconnected from its internal
network, thus becoming high impedance.
WATCHDOG OUTPUT
WDO remains high if there is activity (transi-
tion or pulse) at WDI during the watchdog-
timeout period. The watchdog function is dis-
abled and WDO is a logic high when V
CC
is
less than the reset threshold, or when WDI is an
open circuit. In watchdog mode, if no transi-
tion occurs at WDI during the watchdog-timeout
period, WDO goes low 70ns after the falling
edge of WDPO and remains low until the next
transition at WDI as shown on
Figure 5
. A flip-
flop can force the system into a hardware shut-
down if there are two successive watchdog
faults, shown on
Figure 6
. WDO has a 2 x TTL
output characteristic.
WATCHDOG-PULSE OUTPUT
As described in the preceding section, WDPO
can be used as the clock input to an external D
flip-flop. Upon the absence of a watchdog edge
or pulse at WDI at the end of a watchdog-timeout
period, WDPO will pulse low for 1ms. The fall-
ing edge of WDPO precedes WDO by 70ns.
Since WDO is high when WDPO goes low, the
Q output of the flip-flop remains high as WDO
goes low (
Figure 6
). If the watchdog timer is
not reset by a transition at WDI, WDO remains
low and WDPO clocks a logic low to the Q out-
put, causing the
SP791
to latch in reset. If the
watchdog timer is reset by a transition at WDI,
WDO goes high and the flip-flop's Q output re-
mains high. Thus, a system shutdown is only
caused by two successive watchdog faults.
The internal pull-up resistors associated with
WDO and WDPO connect to V
OUT
. Therefore,
do not connect these outputs directly to CMOS
logic that is powered from V
CC
since, in the ab-
sence of V
CC
(i.e., battery mode), excessive
current will flow from WDO or WDPO through
the protection diode(s) of the CMOS-logic in-
puts to ground.
SELECTING AN ALTERNATIVE
WATCHDOG TIMEOUT PERIOD
SWT input controls the watchdog-timeout pe-
riod. Connecting SWT to V
OUT
selects the in-
ternal 1.6sec watchdog-timeout period. Select
an alternative timeout period by connecting a
capacitor between SWT and GND. Do not leave
SWT floating, and do not connect it to ground.
The following formula determines the watch-
dog-timeout period:
Watchdog Timeout Period = 2.1 x
(capacitor value in nF) ms
This formula is valid for capacitance values
between 4.7 nF and 100nF (see the Watchdog
Timeout vs. Timing Capacitor graph in the
Typi-
cal Operating Characteristics).
CHIP-ENABLE SIGNAL GATING
The
SP791
provides internal gating of chip-en-
able (CE) signals to prevent erroneous data from
corrupting the CMOS RAM in the event of a
power failure. During normal operation, the CE
gate is enabled and passes all CE transitions.
When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupt-
ing the CMOS RAM. The
SP791
uses a series
transmission gate from CE
IN
to CE
OUT
.
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PDF描述 |
|---|---|
| SP791EN | Low Power Microprocessor Supervisory with Battery Switch-Over |
| SP791EP | Low Power Microprocessor Supervisory with Battery Switch-Over |
| SP800LCT | Low Power Microprocessor Supervisory with Battery Switch-Over |
| SP800LEN | Low Power Microprocessor Supervisory with Battery Switch-Over |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP791EN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Low Power Microprocessor Supervisory with Battery Switch-Over |
| SP791EN-L | 功能描述:監(jiān)控電路 LW PWR MICRO 5.5V 25mA-250mA BAT SW/OV RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP791EN-L/TR | 功能描述:監(jiān)控電路 LW PWR MICRO 5.5V 25mA-250mA BAT SW/OV RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP791EP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Low Power Microprocessor Supervisory with Battery Switch-Over |
| SP7AL | 制造商:Hubbell Wiring Device-Kellems 功能描述:ALMOND PAINTED STEEL SGL. RECEPTACLE |
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