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參數(shù)資料
| 型號： | SP9504KS |
| 元件分類： | DAC |
| 英文描述： | QUAD, PARALLEL, WORD INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| 封裝： | 0.350 INCH, PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 184K |
| 代理商： | SP9504KS |
SP9504DS/03
SP9504 Quad, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
6
A
1
A
0
CS
WR1
B1/B2
WR2
XFER
CLR
FUNCTION
0
1
X
Address DAC 1 and load input register
0
1
X
Address DAC 1 and load 4 LSBs
0
1
X
Address DAC 2 and load input register
0
1
0
1
X
Address DAC 2 and load 4 LSBs
1
0
1
X
Address DAC 3 and load input register
1
0
1
X
Address DAC 3 and load 4 LSBs
1
X
Address DAC 4 and load input register
1
0
1
X
Address DAC 4 and load 4 LSBs
X
**
X
1
Transfer data from input registers to DAC registers
X
XXXX
1
Sets all DAC output voltages to 0V
X
1
X
0
Temporarily force all DAC output voltages to 0V,
while CLR is low
X
1
X
Invalid state with any other control line active
X
1
X
Invalid state with any other control line active
X = Don’t care; ** = Don’t care; however, CS and WR1 = 1 will inhibit changes to the input registers.
To load a 12-bit word to the input register of
each DAC, using an 8-bit data bus, the sequence
is as follows:
1) Set XFER=1, B1/B2=1, CLR=1, WR1=1,
WR2=1, CS=1.
2) Set D11 through D4 to the 8 MSB’s of the
desired digital input code.
3) Load the 8 MSB’s of the digital word to
the selected input register by cycling WR1
and CS through the “1” — “0” — “1”
sequence.
4) Reset B1/B2 from “1” —— “0”
5) Set D11 (MSB) through D8 to the 4 LSB’s
of the digital input code.
6) Load the 4 LSB’s by cycling WR1 and CS
through the “1” — “0” — “1” sequence.
Figure 1. Detailed Block Diagram (only one DAC shown)
USING THE SP9504 WITH
DOUBLE-BUFFERED INPUTS
Loading Data
To load a 12-bit word to the input register of
each DAC, using a 12-bit data bus, the sequence
is as follows:
1) Set XFER=1, B1/B2=1, CLR=1, WR1=1,
WR2=1, CS=1.
2) Set A
1 and A0 (the DAC address) to the
desired DAC — 0,0 = DAC
1; 0,1 = DAC2
1,0 = DAC
3; 1,1 = DAC4 .
3) Set D11 (MSB) through D0 (LSB) to the
desired digital input code.
4) Load the word to the selected DAC by
cycling WR1 and CS through the follow-
ing sequence:
“1” — “0” — “1”
5) Repeat sequence for each input register.
DAC
3 TO 7
DECODE
&
5 BITS
8–BIT
LATCH
4-BIT
LATCH
DB11 - DB8
DB7 - DB4
Ref In
–
+
VOUT
44
4
MUX
4
8
12
DB3 - DB0
LATCH
INPUT
REGISTER
DAC
REGISTER
40 K
40 K
Table 2. Control Logic Truth Table
7) Repeat sequence for each input register.
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| SP98608BDG | PARALLEL, 8 BITS INPUT LOADING, 0.002 us SETTLING TIME, 8-BIT DAC, CDIP24 |
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| SPB3 | RECTANGULAR CONNECTOR |
| SPB4 | RECTANGULAR CONNECTOR |
| SPB5 | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| SP9600 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Low Power Voltage Output D/A Converter |
| SP9600AN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Low Power Voltage Output D/A Converter |
| SP9600AS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Low Power Voltage Output D/A Converter |
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