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參數(shù)資料
| 型號(hào)： | SP98608BDG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.002 us SETTLING TIME, 8-BIT DAC, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 312K |
| 代理商： | SP98608BDG |
SP98608
3
Fig.2 SP98608 block diagram
OPERATING NOTES
The pinout of the SP98608 is shown in Fig.1. External
components are the current-setting resistor and decoupling
capacitors.
The DAC has current outputs, with a nominal full-scale
of 40mA, corresponding to a 1V drop across a 25
load.
The actual output current is determined by the on-chip
reference voltage and an off-chip current-setting resistor.
Output current, IOUT, is given by:
IOUT =
x
at full scale
A complementary IOUT is also provided. If single-ended
output operation is employed, it must be ensured that the
complementary output is terminated in an identical manner
to the used output. The setting resistor, RSET, is typically
130
, giving a full-scale output current of 37mA and should
have a temperature coefcient similar to that of the output
load resistor.
Reference
The
reference
supply
is
internally
compensated;
however, to reduce the possibility of instability in some
circuits, it has been bonded out to pin 16, it can therefore be
decoupled to AVEE if required.
Clock
The clock input is ECL 10K compatible. Data at the
device inputs is acquired by the latch on the rising edge of
the clock pulse.
1600
VREF
400 + RLOAD
RSET
Fig.3 Test application circuit
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