參數(shù)資料
型號: SPC5200CBV400
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: MPC5200 Hardware Specifications
中文描述: 400 MHz, RISC PROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272
文件頁數(shù): 49/76頁
文件大?。?/td> 1404K
代理商: SPC5200CBV400
MOTOROLA
MPC5200 Hardware Specifications
49
Electrical and Thermal Characteristics
NOTE:
Output timing was specified at a nominal 50 pF load.
Figure 35 Timing Diagram—I
2
C Input/Output
3.3.14 J1850
See the MPC5200 User Manual [1].
3.3.15 PSC
3.3.15.1
Codec Mode (8,16,24 and 32-bit) / I
2
S Mode
NOTE:
Output timing was specified at a nominal 50 pF load.
1
Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The I
2
C
interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual posi-
tion is affected by the prescale and division values programmed in IFDR.
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
2
3
Table 41 Timing Specifications—8,16, 24 and 32-bit CODEC / I
2
S Master Mode
Sym
Description
Min
Typ
Max
Units
SpecID
1
Bit Clock cycle time, programmed in CCS register
40.0
ns
A15.1
2
Clock pulse width
50
%
1
1
Bit Clock cycle time
A15.2
3
Bit Clock fall time
7.9
ns
A15.3
4
Bit Clock rise time
7.9
ns
A15.4
5
FrameSync valid after clock edge
8.4
ns
A15.5
6
FrameSync invalid after clock edge
8.4
ns
A15.6
7
Output Data valid after clock edge
9.3
ns
A15.7
8
Input Data setup time
6.0
ns
A15.8
1
2
3
4
5
6
7
8
9
SCL
SDA
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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