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參數(shù)資料
| 型號： | SPT7835SIT |
| 廠商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 98K |
| 代理商： | SPT7835SIT |
SPT
7
5/15/01
SPT7835
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical in-
terface requirements when using the SPT7835 in normal
circuit operation. The following sections provide descrip-
tions of the major functions and outline critical perfor-
mance criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
SPT suggests that both the digital and the analog supply
voltages on the SPT7835 be derived from a single analog
supply as shown in figure 2. A separate digital supply
should be used for all interface circuitry. SPT suggests
using this power supply configuration to prevent a possible
latch-up condition on powerup.
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in
the block diagram. The design contains eight identical
successive approximation ADC sections, all operating in
parallel, a 16-phase clock generator, an 11-bit 8:1 digital
output multiplexer, correction logic, and a voltage refer-
ence generator that provides common reference levels for
each ADC section.
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
shown in table II.
VRHF
VRLS
VRLF
VRHS
VIN
CLK
VCAL
DAV
D10
D1
EN
AVDD AGND DGND* DVDD
Ref In
(+4 V)
VIN
CLK IN
Enable/Tri-State
(Enable = Active Low)
Interfacing
Logics
SPT7835
DGND
+
10 F
+5 V
Digital
+5 V
Digital
RTN
3.3/5
L1
NOTES: 1) L1 is to be located as closely to the device as possible.
2) All capacitors are 0.1 F surface-mount unless otherwise specified.
3) L1 is a 10 H inductor or a ferrite bead.
+A5
AGND
+
10 F
+5 V
Analog
+5 V
Analog
RTN
+A5
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
3.3/5
D9
D8
D7
D6
D5
D4
D3
D2
D0
OVDD
OGND
Figure 2 – Typical Interface Circuit
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