參數(shù)資料
型號: SPT7861SCU
廠商: SIGNAL PROCESSING TECHNOLOGIES
元件分類: ADC
英文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, UUC28
封裝: DIE-28
文件頁數(shù): 3/8頁
文件大?。?/td> 91K
代理商: SPT7861SCU
SPT
3
2/10/98
SPT7861
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, VIN=0 to 4 V, fS=40 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
TEST
SPT7861
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
Dynamic Performance
Signal-to-Noise and Distortion
(SINAD)
fIN=3.58 MHz
VI
54
57
dB
fIN=10.3 MHz
VI
53
55
dB
Spurious Free Dynamic Range
fIN=1.0 MHz
V
64
dB
Differential Phase
V
±0.3
Degree
Differential Gain
V
±0.3
%
Intermodulation Distortion
TBD
dB
Inputs
Logic 1 Voltage
VI
2.0
V
Logic 0 Voltage
VI
0.8
V
Maximum Input Current Low
VI
-10
+10
A
Maximum Input Current High
VI
-10
+10
A
Input Capacitance
V
+5
pF
Digital Outputs
Logic 1 Voltage
IOH = 0.5 mA
VI
3.5
V
Logic 0 Voltage
IOL = 1.6 mA
VI
0.4
V
tRISE
15 pF load
V
10
ns
tFALL
15 pF load
V
10
ns
Output Enable to Data Output Delay
20 pF load, TA = +25 °C
V
10
ns
50 pF load over temp.
V
22
ns
Power Supply Requirements
Voltages
OVDD
IV
3.0
5.0
V
DVDD
IV
4.75
5.0
5.25
V
AVDD
IV
4.75
5.0
5.25
V
Currents
AIDD
VI
14
22
mA
DIDD
VI
18
23
mA
Power Dissipation
VI
160
225
mW
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
TEST LEVEL
I
II
III
IV
V
VI
DESCRIPTION
PARAMETERS
MIN
TYP
MAX
UNITS
Conversion Time
tC
tCLK
ns
Clock Period
tCLK
25
ns
Clock High Duty Cycle
tCH
40
50
60
%
Clock Low Duty Cycle
tCL
40
50
60
%
Clock to Output Delay (15 pF Load)
tOD
17
ns
Clock to DAV
tS
10
ns
Table I - Timing Parameters
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