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參數(shù)資料
| 型號(hào)： | SPT7870SIQ |
| 廠商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP44 |
| 封裝： | CERQUAD-44 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 67K |
| 代理商： | SPT7870SIQ |
SPT
5
9/8/98
SPT7870
DIGITAL OUTPUT DATA TIMING
The data is presented on the output pins two clock cycles after
the input is sampled with an additional output delay of
typically 3 ns. The data is held valid for one clock cycle. Refer
to the timing diagram shown in figure 1.
DIGITAL OUTPUT CONTROL PINS - MINV, LINV
Two digital output control pins control the digital output format.
See table III. The MINV pin is a CMOS/TTL-compatible input.
It inverts the most-significant bit (D9) when tied to +5 V. The
MSB (D9) is noninverted when MINV is tied to ground or
floated. The MINV pin is internally pulled down to ground.
The LINV pin is a CMOS/TTL-compatible input. It inverts the
least-significant bits (D8 through D0) when tied to +5 V. The
least-significant bits (D8 through D0) are noninverted when
LINV is tied to ground or floated. The LINV pin is internally
pulled down to ground.
Table III - Data Output Bits
MINV
LINV
Description of Data
0 V
Binary (Noninverted)
0 V
+5 V
Two's Complement (Inverted)
+5 V
0 V
Two's Complement (Noninverted)
+5 V
Binary (Inverted)
ECL AND PECL DIGITAL OUTPUT LEVELS
The SPT7870 supports ECL (10K and 100K compatible) and
PECL logic levels. It has single-ended output drive capability.
ECL termination resistors of 50
to -2 V are required as
shown in the typical interface circuit in figure 2. To interface
to PECL logic levels, supply +5 V to DGND and terminate the
digital outputs through 50
resistors to +3 V.
THERMAL MANAGEMENT
SPT recommends that a heat sink be used for this device to
ensure rated performance. A heat sink in still air provides
adequate thermal performance under laboratory tests. Air
flow may be required for operation at elevated ambient
temperature. SPT recommends that the junction tempera-
ture be maintained under +150
°C.
The thermal impedance values for the cerquad package are
θJC = 3.3 °C/W and θJA = 70 °C/W (junction to ambient in still
air with no heat sink).
than 80 MSPS, additional gains in dynamic performance of
the device may be obtained by adjusting the clock duty cycle.
Typically, operation between 55 to 60% duty cycle will yield
improved results.
INTERNAL VOLTAGE REFERENCE
The SPT7870 incorporates an on-chip voltage reference.
The top and bottom reference voltages are each internally
tied to their respective top and bottom of the internal refer-
ence ladder. The pins for the voltage references and the
ladder (including the center of the ladder) are brought out to
pins on the device for decoupling purposes only (pins VT, VM,
and VB). A .01 F capacitor should be used on each pin and
tied to AGND. See the typical interface circuit (figure 2).
The internal voltage reference and the internal error correc-
tion logic eliminate the need for driving externally the voltage
reference ladder. In fact,
the voltage reference ladder should
not be driven with an external voltage reference source as the
internal error correction circuitry already compensates for the
internal voltage and no improvement will result.
DIGITAL OUTPUTS
DIGITAL OUTPUT DATA FORMAT - D0 - D9
D0 is the least-significant bit for the digital data output, and D9
is the most-significant bit. Four data output formats are
available and are controlled by the MINV and LINV pins.
Table III shows the four possible output formats possible as
a function of MINV and LINV. Table II shows the output coding
data format versus analog input voltage relationship.
Table II - Output Coding Data Format
VIN
D10 D9…D0 (Binary*) D9…D0 (2's Comp*)
>+1.0 V
1
11 1111 1111
01 1111 1111
(+FS)
0
11 1111 1111
01 1111 1111
+1.0 V -1 LSB
0
11 1111 1110
01 1111 1110
0.0 V
0
10 0000 0000
00 0000 0000
0
01 1111 1111
11 1111 1111
-1.0 V +1 LSB
0
00 0000 0001
10 0000 0001
(-FS)
0
00 0000 0000
10 0000 0000
<-1.0 V
0
00 0000 0000
10 0000 0000
*Refer to table III for possible output formats.
OVERRANGE BIT - D10
D10 is the overrange bit which is asserted whenever the
analog input signal exceeds the positive full scale input by
1 LSB. When this condition occurs the D10 bit will be asserted
to logic high and remain high continuously until the overrange
condition is removed from the input.
All other output signals will also stay at their maximum
encoded output throughout this condition. D10 is not as-
serted for an underscale condition when the input exceeds
the negative full scale.
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