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參數(shù)資料
| 型號： | SQ930C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High-Speed USB 2.0 Video Camera Controller |
| 中文描述： | 高速USB 2.0視頻攝像機(jī)控制器 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 431K |
| 代理商： | SQ930C |
S
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Q
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C
C
High-Speed USB 2.0 Video Camera Controller
2.2.3
LFBGA 64 Pin Descriptions
T
ABLE
2–2: P
OWER
S
UPPLY
P
INS
(LFBGA 64)
PIN NO
NAME
I/O
DESCRIPTION
C3
AGND2
PWR
Analog ground
D2
AVCC2
PWR
Power, Analog AVCC=3.3
Analog ground
C4
AGND3
PWR
D3
AVCC3
PWR
Power, Analog AVCC=3.3
C5
VCCIO
PWR
PWR
Power, Digital VCC=3.3
D5
GND
Digital ground
B5
VCCK
PWR
Power, Digital VCCK=2.5
D6
GND
PWR
Digital ground
C6
VCCIO
PWR
Power, Digital VCC=3.3
D4
ZREGO3.3
PWR
Power, Digital VCC=3.3
F4
ZREGO2.5
PWR
Power, Digital VCCK=2.5
E5
GND
PWR
Digital ground
B6
VCCK
PWR
Power, Digital VCCK=2.5
E4
GND
PWR
Digital ground
B3
AVCC1
PWR
Analog AVCC=3.3
B4
AGND1
PWR
Analog ground
T
ABLE
2–3: S
YSTEM
P
INS
(LFBGA 64)
PIN NO
NAME
I/O
DESCRIPTION
A6
NRES
I
Digital input Pull high to force ASIC normal action, low will into reset state.
A4
XOSCI
I
12M Crystal in
A3
XOSCO
O
12M Crystal out
T
ABLE
2–4: 8032 CPU I
NTERFACE
P
INS
(LFBGA 64)
PIN NO
NAME
I/O
DESCRIPTION
D1
CPU_P3.1
I/O
Port 3.1 bi-directional I/O port
E3, E1, F1, E2,
F2, G1, H1
CPU_P2.6~
CPU_P2.0
O
Microprocessor High Address Bus
H2
CPU_PSEN
O
Program Store Enable is the read strobe to external program memory.
G2, F3, H3, G3
CPU_P1.3~
CPU_P1.0
I/O
Port 1.3~ Port 1.0 is an 4-bit bi-directional I/O port
H4, G4, G5, H5,
F5, G6, H6, H7
CPU_P0.7~
CPU_P0.0
I/O
Microprocessor Data / Low Address Bus
H8
CPU_ALE
O
Address Latch Enable output pulse for latching the low byte of the address
during accesses to external memory.
Subject to Change Without Notice.
PAGE 9
Version 1.3 - April 22
nd
, 2005
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