參數(shù)資料
型號: SRC4194
英文描述: 4-Channel, Asynchronous Sample Rate Converter
中文描述: 4通道,異步采樣率轉(zhuǎn)換器
文件頁數(shù): 21/40頁
文件大?。?/td> 502K
代理商: SRC4194
"#$%#
SBFS025A JUNE 2004 REVISED JULY 2004
www.ti.com
21
Operation for SRC A and SRC B is identical. Audio data
is received at the input serial port, clocked by either the
audio source device in Slave mode, or by the SRC4194 in
Master mode. The output port data is clocked by either the
audio output device in Slave mode, or by the SRC4194 in
Master mode. The input data is passed through
interpolation filters that upsample the data, which is then
passed on to the re-sampler. The rate estimator compares
the input and output sampling frequencies by comparing
LRCKI, LRCKO, and a reference clock. The results of the
rate estimation are utilized to configure the re-sampler
coefficients and data pointers.
The output of the re-sampler is passed on to either the
decimation filter or direct downsampler function. The
decimation filter performs downsampling and anti-alias
filtering functions, and is required when the output
sampling frequency is equal to or lower than the input
sampling frequency. The direct downsampler function
does not provide any filtering, and may be used in cases
when the output sampling frequency is greater than the
input sampling frequency. The advantage of the direct
downsampling function is a significant reduction in the
group delay associated with the decimation function,
allowing lower latency processing.
REFERENCE CLOCK
The SRC4194 includes two reference clock inputs, one
each for SRC A and SRC B. The reference clocks are
applied at the RCKIA (pin 20) and RCKIB (pin 29) inputs,
respectively. The reference clock is required for the rate
estimator function, as well as for the input or output serial
ports when configured in Master mode.
Figure 2 illustrates the reference clock connections and
requirements for the SRC4194. When either the input or
output port is configured in Master mode, the reference
clock may operate at 128f
s
, 256f
s
, or 512f
s
, where f
s
is the
desired sampling rate for the Master mode port. When both
the input and output port are configured in Slave mode, the
reference clock does not have to be a multiple of the input
or output sampling rates. The maximum reference clock
input frequency is 50MHz for RCKIA and RCKIB.
t
RCKIP
t
RCKIH
t
RCKIL
RCKI
SRC4194
RCKI2
FromExternal
Clock Source(s)
50MHz Max
29
RCKI1
20
t
RCKIP
> 20ns min
t
RCKIH
> 0.4 t
RCKIP
t
RCKIL
> 0.4 t
RCKIP
Figure 2. Reference Clock Input Connections and
Timing Requirements
RESET AND POWER-DOWN OPERATION
The SRC4194 may be reset using the RST input (pin 21).
There is no internal power on reset, so the user should
force a reset sequence after power up in order to initialize
the device. In order to force a reset, the reference clock
inputs must be active, with external clock sources
supplying a valid reference clock signal (refer to Figure 2).
The user must assert RST low for a minimum of 500ns and
then bring RST high again to force a reset. The reset
function affects both SRC A and SRC B. Figure 3 shows
the reset timing for the SRC4194.
In Software mode, there is a 500ms delay after the RST
rising edge due to internal logic requirements. The
customer should wait a minimum 500ms after the RST
rising edge before attempting to write to the SPI port of the
SRC4194 in Software mode.
RST
RCKIA
RCKIB
t
RSTL
> 500ns
Figure 3. Reset Pulsewidth Requirement
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