參數(shù)資料
型號: SRC4194
英文描述: 4-Channel, Asynchronous Sample Rate Converter
中文描述: 4通道,異步采樣率轉換器
文件頁數(shù): 32/40頁
文件大?。?/td> 502K
代理商: SRC4194
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SBFS025A JUNE 2004 REVISED JULY 2004
www.ti.com
32
Register 4. Digital Output Attenuation Register—Left Channel
D7
(MSB)
AL7
D6
AL6
D5
AL5
D4
AL4
D3
AL3
D2
AL2
D1
AL1
D0
(LSB)
AL0
This register is utilized to program the digital output attenuation for the Left output channel of the
corresponding SRC section.
Register defaults to 00h, or 0dB (unity gain).
Output Attenuation (dB) = N
×
0.5, where N = AL[7:0]
DEC
Register 5. Digital Output Attenuation Register—Right Channel
D7
(MSB)
AR7
D6
AR6
D5
AR5
D4
AR4
D3
AR3
D2
AR2
D1
AR1
D0
(LSB)
AR0
This register is utilized to program the digital output attenuation for the Right output channel of the
corresponding SRC section. When the TRACK bit in Control Register 1 is set to 1, the Left Channel
attenuation setting will also be used to set the Right Channel attenuation.
Register defaults to 00h, or 0dB (unity gain).
Output Attenuation (dB) = N
×
0.5, where N = AR[7:0]
DEC
Register 6. Sampling Ratio (read only)
D7
(MSB)
SRI4
D6
SRI3
D5
SRI2
D4
SRI1
D3
SRI0
D2
D1
SRF9
D0
(LSB)
SRF8
SRF10
Register 7. Sampling Ratio (read only)
D7
(MSB)
SRF7
D6
SRF6
D5
SRF5
D4
SRF4
D3
SRF3
D2
SRF2
D1
SRF1
D0
(LSB)
SRF0
The contents of Register 6 and Register 7 indicate the input-to-output sampling ratio, and can be used to
determine either the input or output sampling rates when one of the two rates is known.
Bits SRI[4:0] comprise the integer portion of the input-to-output sampling ratio.
Bits SRF[10:0] comprise the fractional portion of the input-to-output sampling ratio.
The contents of Register 6 and Register 7 are updated when Register 6 is read. Register 6 must always be
read first in order to obtain the latest ratio data for both registers.
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