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SBFS025A JUNE 2004 REVISED JULY 2004
www.ti.com
6
PIN DESCRIPTIONS
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24, 25
26
27, 28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(1)Disabled in Software control mode.
(2)Disabled in Hardware control mode.
NAME
IFMTA0
IFMTA1
IFMTA2
OFMTA0
OFMTA1
OWLA0
OWLA1
BYPA
LGRPA0
LGRPA1
DDNA
DEMA0
DEMA1
MODEA0
MODEA1
MODEA2
RATIOA
RDYA
MUTEA
RCKIA
RST
H/S
DGND
VDD33
REGEN
VDD18
RCKIB
MUTEB
RDYB
RATIOB
MODEB2 or CDIN
MODEB1 or CCLK
MODEB0 or CS
DEMB1 or CDOUT
DEMB0
DDNB
LGRPB1
LGRPB0
BYPB
OWLB1
OWLB0
OFMTB1
OFMTB0
IFMTB2
IFMTB1
IFMTB0
SDOUTB
BCKOB
LRCKOB
TDMIB
BCKIB
LRCKIB
SDINB
VIO
DGND
SDINA
LRCKIA
BCKIA
TDMIA
LRCKOA
BCKOA
SDOUTA
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Ground
Power
Input
Power
Input
Input
Output
Output
Input
Input
Input
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
I/O
I/O
Input
I/O
I/O
Input
Power
Ground
Input
I/O
I/O
Input
I/O
I/O
Output
DESCRIPTION
SRC A Audio Input Data Format(1)
SRC A Audio Input Data Format(1)
SRC A Audio Input Data Format(1)
SRC A Audio Output Data Format(1)
SRC A Audio Output Data Format(1)
SRC A Audio Output Data Word Length(1)
SRC A Audio Output Data Word Length(1)
SRC A Bypass Mode (Active High)
SRC A Low Group Delay Mode(1)
SRC A Low Group Delay Mode(1)
SRC A Direct Downsampling Mode (Active High)(1)
SRC A Digital De-Emphasis Filter Mode(1)
SRC A Digital De-Emphasis Filter Mode(1)
SRC A Serial Port Mode(1)
SRC A Serial Port Mode(1)
SRC A Serial Port Mode(1)
SRC A Ratio Flag
SRC A Ready Flag (Active Low)
SRC A Output Soft Mute
SRC A Reference Clock
Reset and Power-Down (Active Low)
Control Mode (0 = Software, 1 = Hardware)
Digital Ground
Core Supply, +3.3V. Required when REGEN is high. When REGEN is low, VDD33 must be left unconnected.
Voltage Regulator Enable (Active High)
Core Supply, +1.8V. Required when REGEN is low. When REGEN is high, VDD18 must be left unconnected.
SRC B Reference Clock
SRC B Output Soft Mute
SRC B Ready Flag (Active Low)
SRC B Ratio Flag
SRC B Serial Port Mode(1) or SPI Port Serial Data Input(2)
SRC B Serial Port Mode(1) or SPI Port Data Clock(2)
SRC B Serial Port Mode(1) or SPI Port Chip Select (Active Low)(2)
SRC B Digital De-Emphasis Filter Mode(1) or SPI Port Serial Data Output(2)
SRC B Digital De-Emphasis Filter Mode(1)
SRC B Direct Downsampling Mode (Active High)(1)
SRC B Low Group Delay Mode(1)
SRC B Low Group Delay Mode(1)
SRC B Bypass Mode (Active High)
SRC B Audio Output Data Word Length(1)
SRC B Audio Output Data Word Length(1)
SRC B Audio Output Data Format(1)
SRC B Audio Output Data Format(1)
SRC B Audio Input Data Format(1)
SRC B Audio Input Data Format(1)
SRC B Audio Input Data Format(1)
SRC B Audio Output Data
SRC B Audio Output Bit Clock
SRC B Audio Output Left/Right or Word Clock
SRC B TDM Input Data (TDM Format Only)
SRC B Audio Input Bit Clock
SRC B Audio Input Left/Right or Word Clock
SRC B Audio Input Data
Digital I/O Supply, +1.65V to +3.6V
Digital Ground
SRC A Audio Input Data
SRC A Audio Input Left/Right or Word Clock
SRC A Audio Input Bit Clock
SRC A TDM Input Data (TDM Format Only)
SRC A Audio Output Left/Right or Word Clock
SRC A Audio Output Bit Clock
SRC A Audio Output Data