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參數(shù)資料
| 型號： | SRC4194IPAGR |
| 英文描述： | 4-Channel, Asynchronous Sample Rate Converter |
| 中文描述： | 4通道，異步采樣率轉(zhuǎn)換器 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 502K |
| 代理商： | SRC4194IPAGR |
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SBFS025A JUNE 2004 REVISED JULY 2004
www.ti.com
22
The SRC4194 also supports two power-down modes. The
entire SRC4194 may be powered down by forcing and
holding the RST input low. This is referred to as a Hard
Power-Down, and the SRC4194 consumes the least
amount of power in this mode.
In Software mode, there is an additional Soft Power-Down
available, utilizing the PDN bit in Control Register 1. Soft
Power-Down is enabled when the PDN bit is set to 0. Since
SRC A and SRC B have their own separate register banks,
they may be set to Soft Power-Down mode individually.
During Soft Power-Down, the SPI port and control
registers remain active for write and read access. The
internal voltage regulator also remains active if the
REGEN pin is forced high and +3.3V is applied at the
VDD33 pin.
Soft Power-Down mode consumes more power than the
Hard Power-Down mode. Refer to the Electrical
Characteristics tables in this data sheet for supply current
and power dissipation specifications for both modes.
Finally, there is one very important item to remember when
using Software mode. The default state of the PDN bit is
0, meaning that the SRC4194 will default to the Soft
Power-Down state for both SRC A and SRC B after power
up or reset. The user must set the PDN bit to 1 for both the
SRC A and SRC B control register banks in order to enable
normal operation for both SRC sections.
AUDIO SERIAL PORT MODES
The SRC4194 supports seven serial port modes for the
SRC A and SRC B sections, which are shown in Table 1.
In Hardware mode, the audio port mode is selected using
the MODEA0 (pin 14), MODEA1 (pin 15), and MODEA2
(pin 16) inputs for SRC A, while the MODEB0 (pin 35),
MODEB1 (pin 34), and MODEB2 (pin 33) inputs are used
for SRC B.
In Software mode, the audio serial port modes are
selected using the MODE[2:0] bits in Control Register 1 for
the SRC A and SRC B register banks. The default setting
for Software mode is both input and output ports set to
Slave mode.
In Slave mode, the port LRCK and BCK clocks are
configured as inputs, and receive their clocks from an
external audio device. In Master mode, the LRCK and
BCK clocks are configured as outputs, being derived from
the reference clock input for the corresponding SRC
section, either RCKIA or RCKIB. Only one port can be set
to Master mode at any given time, as indicated in Table 1.
Table 1. Setting the Serial Port Modes (x = A or B)
MODEx2
0
MODEx1
0
MODEx0
0
SERIAL PORT MODE
Both Input and Output Ports are
Slave mode
Output Port is Master Mode with
RCKIx = 128fS
Output Port is Master Mode with
RCKIx = 512fS
Output Port is Master Mode with
RCKIx = 256fS
Both Input and Output Ports are
Slave mode
Input Port is Master Mode with
RCKIx = 128fS
Input Port is Master Mode with
RCKIx = 512fS
Input Port is Master Mode with
RCKIx = 256fS
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
INPUT PORT OPERATION
The audio input port is a three-wire synchronous serial
interface that may operate in either Slave or Master mode.
The SDINA (pin 58) and SDINB (pin 55) are the serial
audio data inputs for SRC A and SRC B, respectively.
Audio data is input at these pins in one of three standard
audio data formats: Philips I
2
S, Left-Justified, or
Right-Justified. The audio data word length may be up to
24-bits for I
2
S and Left-Justified formats, while the
Right-Justified format supports 16-, 18-, 20-, or 24-bit data.
The audio data is always Binary Two’s Complement with
the MSB first. Refer to Figure 4 for the input data formats
and Figure 5 for the critical timing parameters, which are
also listed in the Electrical Characteristics table.
The bit clock is either an input or output at BCKIA (pin 60)
and BCKIB (pin 53). In Slave mode, the bit clock is
configured as an input pin, and may operate at rates from
32f
s
to 128f
s
,with a minimum of one clock cycle per data
bit. In Master mode, bit clock operates at a fixed rate of
64f
s
.
The left/right word clock, LRCKIA (pin 59) and LRCKIB
(pin 54), may be configured as an input or output pin. In
Slave mode, left/right clock is an input pin, while in Master
mode the left/right clock is an output pin. In either case, the
clock rate is equal to f
s
, the input sampling frequency. The
LRCKI duty cycle is fixed to 50% for Master mode
operation.
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| SRC4194IPAGRG4 | 功能描述:音頻采樣頻率轉(zhuǎn)換器 4-Ch Asynch Sample Rate Converter RoHS:否 制造商:Texas Instruments THD + 噪聲:- 140 dB 接口:I2C, SPI 工作電源電壓:1.65 V to 2 V / 3 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:TQFP-48 安裝風(fēng)格:SMD/SMT |
| SRC4194IPAGT | 功能描述:音頻采樣頻率轉(zhuǎn)換器 4-Channel Async Sample Rate Conv RoHS:否 制造商:Texas Instruments THD + 噪聲:- 140 dB 接口:I2C, SPI 工作電源電壓:1.65 V to 2 V / 3 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:TQFP-48 安裝風(fēng)格:SMD/SMT |
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