參數(shù)資料
型號: SRC4194IPAGR
英文描述: 4-Channel, Asynchronous Sample Rate Converter
中文描述: 4通道,異步采樣率轉(zhuǎn)換器
文件頁數(shù): 30/40頁
文件大小: 502K
代理商: SRC4194IPAGR
"#$%#
SBFS025A JUNE 2004 REVISED JULY 2004
www.ti.com
30
Register 2. Digital Filter Control Register
D7
(MSB)
0
D6
0
D5
0
D4
D3
D2
DDN
D1
D0
(LSB)
LGRP0
DEM1
DEM0
LGRP1
LGRP0
Interpolation Filter Group Delay
LGRP1
These bits are used to select the number of input samples to be stored in the data buffer before the re-sampler
starts to process the data. This has a direct impact on the group delay or latency of the interpolation filter.
LGRP1
0
0
1
1
LGRP0
0
1
0
1
GROUP DELAY
64 Samples (default)
32 Samples
16 Samples
8 Samples
DDN
Decimation Filtering/Direct Downsampling
The DDN bit is used to enable or disable the direct downsampling function of the decimation block.
DDN
0
DECIMATION FILTER OPERATION
Decimation filter enabled. (default)
(Must be used when fsOUT is less than or equal to fsIN.)
Direct downsampling enabled without filtering.
(May be enabled when fsOUT is greater than fsIN.)
1
DEM0
Digital De-Emphasis Filtering
DEM1
These bits are used to configure the digital de-emphasis filter function.
DEM1
0
0
1
1
DEM0
0
1
0
1
DE-EMPHASIS FILTER
Disabled (default)
48kHz Input Sampling Rate
44.1kHz Input Sampling Rate
32kHz Input Sampling Rate
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